Lines Matching refs:half

4 define <4 x half> @load_64(<4 x half>* nocapture readonly %a) #0 {
8   %0 = load <4 x half>, <4 x half>* %a, align 8
9   ret <4 x half> %0
13 define <8 x half> @load_128(<8 x half>* nocapture readonly %a) #0 {
17   %0 = load <8 x half>, <8 x half>* %a, align 16
18   ret <8 x half> %0
22 define <4 x half> @load_dup_64(half* nocapture readonly %a) #0 {
26   %0 = load half, half* %a, align 2
27   %1 = insertelement <4 x half> undef, half %0, i32 0
28   %2 = shufflevector <4 x half> %1, <4 x half> undef, <4 x i32> zeroinitializer
29   ret <4 x half> %2
33 define <8 x half> @load_dup_128(half* nocapture readonly %a) #0 {
37   %0 = load half, half* %a, align 2
38   %1 = insertelement <8 x half> undef, half %0, i32 0
39   %2 = shufflevector <8 x half> %1, <8 x half> undef, <8 x i32> zeroinitializer
40   ret <8 x half> %2
44 define <4 x half> @load_lane_64(half* nocapture readonly %a, <4 x half> %b) #0 {
48   %0 = load half, half* %a, align 2
49   %1 = insertelement <4 x half> %b, half %0, i32 2
50   ret <4 x half> %1
54 define <8 x half> @load_lane_128(half* nocapture readonly %a, <8 x half> %b) #0 {
58   %0 = load half, half* %a, align 2
59   %1 = insertelement <8 x half> %b, half %0, i32 5
60   ret <8 x half> %1
64 define void @store_64(<4 x half>* nocapture %a, <4 x half> %b) #1 {
68   store <4 x half> %b, <4 x half>* %a, align 8
73 define void @store_128(<8 x half>* nocapture %a, <8 x half> %b) #1 {
77   store <8 x half> %b, <8 x half>* %a, align 16
82 define void @store_lane_64(half* nocapture %a, <4 x half> %b) #1 {
86   %0 = extractelement <4 x half> %b, i32 2
87   store half %0, half* %a, align 2
91 define void @store_lane0_64(half* nocapture %a, <4 x half> %b) #1 {
95   %0 = extractelement <4 x half> %b, i32 0
96   store half %0, half* %a, align 2
100 define void @storeu_lane0_64(half* nocapture %a, <4 x half> %b) #1 {
104   %0 = getelementptr half, half* %a, i64 -1
105   %1 = extractelement <4 x half> %b, i32 0
106   store half %1, half* %0, align 2
110 define void @storero_lane_64(half* nocapture %a, <4 x half> %b, i64 %c) #1 {
114   %0 = getelementptr half, half* %a, i64 %c
115   %1 = extractelement <4 x half> %b, i32 2
116   store half %1, half* %0, align 2
120 define void @storero_lane0_64(half* nocapture %a, <4 x half> %b, i64 %c) #1 {
124   %0 = getelementptr half, half* %a, i64 %c
125   %1 = extractelement <4 x half> %b, i32 0
126   store half %1, half* %0, align 2
131 define void @store_lane_128(half* nocapture %a, <8 x half> %b) #1 {
135   %0 = extractelement <8 x half> %b, i32 5
136   store half %0, half* %a, align 2
140 define void @store_lane0_128(half* nocapture %a, <8 x half> %b) #1 {
144   %0 = extractelement <8 x half> %b, i32 0
145   store half %0, half* %a, align 2
149 define void @storeu_lane0_128(half* nocapture %a, <8 x half> %b) #1 {
153   %0 = getelementptr half, half* %a, i64 -1
154   %1 = extractelement <8 x half> %b, i32 0
155   store half %1, half* %0, align 2
159 define void @storero_lane_128(half* nocapture %a, <8 x half> %b, i64 %c) #1 {
163   %0 = getelementptr half, half* %a, i64 %c
164   %1 = extractelement <8 x half> %b, i32 4
165   store half %1, half* %0, align 2
169 define void @storero_lane0_128(half* nocapture %a, <8 x half> %b, i64 %c) #1 {
173   %0 = getelementptr half, half* %a, i64 %c
174   %1 = extractelement <8 x half> %b, i32 0
175   store half %1, half* %0, align 2
180 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
181 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
182 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
183 declare void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
184 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
185 …re void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x …
186 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>*)
187 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>*)
188 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 …
189 declare void @llvm.aarch64.neon.st2.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>*)
190 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*)
191 …re void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x …
194 define { <4 x half>, <4 x half> } @load_interleave_64_2(<4 x half>* %a) #0 {
198   %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>* %a)
199   ret { <4 x half>, <4 x half> } %0
203 define { <4 x half>, <4 x half>, <4 x half> } @load_interleave_64_3(<4 x half>* %a) #0 {
207 …%0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x ha…
208   ret { <4 x half>, <4 x half>, <4 x half> } %0
212 define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_interleave_64_4(<4 x half>* %a) #0 {
216 …%0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v…
217   ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0
221 define void @store_interleave_64_2(<4 x half>* %a, <4 x half> %b, <4 x half> %c) #0 {
225   tail call void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half>* %a)
230 define void @store_interleave_64_3(<4 x half>* %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) #0 {
234 …call void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x h…
239 define void @store_interleave_64_4(<4 x half>* %a, <4 x half> %b, <4 x half> %c, <4 x half> %d, <4 …
243 …d @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e,…
248 define { <8 x half>, <8 x half> } @load_interleave_128_2(<8 x half>* %a) #0 {
252   %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>* %a)
253   ret { <8 x half>, <8 x half> } %0
257 define { <8 x half>, <8 x half>, <8 x half> } @load_interleave_128_3(<8 x half>* %a) #0 {
261 …%0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x ha…
262   ret { <8 x half>, <8 x half>, <8 x half> } %0
266 define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_interleave_128_4(<8 x half>* %a) #0…
270 …%0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v…
271   ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0
275 define void @store_interleave_128_2(<8 x half>* %a, <8 x half> %b, <8 x half> %c) #0 {
279   tail call void @llvm.aarch64.neon.st2.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half>* %a)
284 define void @store_interleave_128_3(<8 x half>* %a, <8 x half> %b, <8 x half> %c, <8 x half> %d) #0…
288 …call void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x h…
293 define void @store_interleave_128_4(<8 x half>* %a, <8 x half> %b, <8 x half> %c, <8 x half> %d, <8…
297 …d @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e,…
302 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half*)
303 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half*)
304 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0f16(half…
305 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half*)
306 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half*)
307 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0f16(half…
310 define { <4 x half>, <4 x half> } @load_dup_64_2(half* %a) #0 {
314   %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half* %a)
315   ret { <4 x half>, <4 x half> } %0
319 define { <4 x half>, <4 x half>, <4 x half> } @load_dup_64_3(half* %a) #0 {
323 …%0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half* %a)
324   ret { <4 x half>, <4 x half>, <4 x half> } %0
328 define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_dup_64_4(half* %a) #0 {
332 …%0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0…
333   ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0
337 define { <8 x half>, <8 x half> } @load_dup_128_2(half* %a) #0 {
341   %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half* %a)
342   ret { <8 x half>, <8 x half> } %0
346 define { <8 x half>, <8 x half>, <8 x half> } @load_dup_128_3(half* %a) #0 {
350 …%0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half* %a)
351   ret { <8 x half>, <8 x half>, <8 x half> } %0
355 define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_dup_128_4(half* %a) #0 {
359 …%0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0…
360   ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0
365 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2lane.v4f16.p0f16(<4 x half>, <4 x half>, i…
366 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3lane.v4f16.p0f16(<4 x half>, <…
367 … <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4lane.v4f16.p0f16(<4 x half…
368 declare void @llvm.aarch64.neon.st2lane.v4f16.p0f16(<4 x half>, <4 x half>, i64, half*)
369 declare void @llvm.aarch64.neon.st3lane.v4f16.p0f16(<4 x half>, <4 x half>, <4 x half>, i64, half*)
370 … void @llvm.aarch64.neon.st4lane.v4f16.p0f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, i64, …
371 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2lane.v8f16.p0f16(<8 x half>, <8 x half>, i…
372 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3lane.v8f16.p0f16(<8 x half>, <…
373 … <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4lane.v8f16.p0f16(<8 x half…
374 declare void @llvm.aarch64.neon.st2lane.v8f16.p0f16(<8 x half>, <8 x half>, i64, half*)
375 declare void @llvm.aarch64.neon.st3lane.v8f16.p0f16(<8 x half>, <8 x half>, <8 x half>, i64, half*)
376 … void @llvm.aarch64.neon.st4lane.v8f16.p0f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, i64, …
379 define { <4 x half>, <4 x half> } @load_lane_64_2(half* %a, <4 x half> %b, <4 x half> %c) #0 {
383 …%0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2lane.v4f16.p0f16(<4 x half> %b, <4…
384   ret { <4 x half>, <4 x half> } %0
388 define { <4 x half>, <4 x half>, <4 x half> } @load_lane_64_3(half* %a, <4 x half> %b, <4 x half> %…
392 … call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3lane.v4f16.p0f16(<4 x half> %b,…
393   ret { <4 x half>, <4 x half>, <4 x half> } %0
397 define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_lane_64_4(half* %a, <4 x half> %b, …
401 …half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4lane.v4f16.p0f16(<4 x half> %b, …
402   ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0
406 define void @store_lane_64_2(half* %a, <4 x half> %b, <4 x half> %c) #0 {
410 …tail call void @llvm.aarch64.neon.st2lane.v4f16.p0f16(<4 x half> %b, <4 x half> %c, i64 2, half* %…
415 define void @store_lane_64_3(half* %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) #0 {
419 …l void @llvm.aarch64.neon.st3lane.v4f16.p0f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, i64 2, …
424 define void @store_lane_64_4(half* %a, <4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e) …
428 …llvm.aarch64.neon.st4lane.v4f16.p0f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e, …
433 define { <8 x half>, <8 x half> } @load_lane_128_2(half* %a, <8 x half> %b, <8 x half> %c) #0 {
437 …%0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2lane.v8f16.p0f16(<8 x half> %b, <8…
438   ret { <8 x half>, <8 x half> } %0
442 define { <8 x half>, <8 x half>, <8 x half> } @load_lane_128_3(half* %a, <8 x half> %b, <8 x half> …
446 … call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3lane.v8f16.p0f16(<8 x half> %b,…
447   ret { <8 x half>, <8 x half>, <8 x half> } %0
451 define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_lane_128_4(half* %a, <8 x half> %b,…
455 …half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4lane.v8f16.p0f16(<8 x half> %b, …
456   ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0
460 define void @store_lane_128_2(half* %a, <8 x half> %b, <8 x half> %c) #0 {
464 …tail call void @llvm.aarch64.neon.st2lane.v8f16.p0f16(<8 x half> %b, <8 x half> %c, i64 2, half* %…
469 define void @store_lane_128_3(half* %a, <8 x half> %b, <8 x half> %c, <8 x half> %d) #0 {
473 …l void @llvm.aarch64.neon.st3lane.v8f16.p0f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, i64 2, …
478 define void @store_lane_128_4(half* %a, <8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e)…
482 …llvm.aarch64.neon.st4lane.v8f16.p0f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e, …
487 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0v4f16(<4 x half>*)
488 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0v4f16(<4 x half>*)
489 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0v4f16(<…
490 declare void @llvm.aarch64.neon.st1x2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
491 declare void @llvm.aarch64.neon.st1x3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
492 … void @llvm.aarch64.neon.st1x4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x …
493 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x2.v8f16.p0v8f16(<8 x half>*)
494 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x3.v8f16.p0v8f16(<8 x half>*)
495 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x4.v8f16.p0v8f16(<…
496 declare void @llvm.aarch64.neon.st1x2.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>*)
497 declare void @llvm.aarch64.neon.st1x3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*)
498 … void @llvm.aarch64.neon.st1x4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x …
501 define { <4 x half>, <4 x half> } @load_64_2(<4 x half>* %a) #0 {
505   %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0v4f16(<4 x half>* %a)
506   ret { <4 x half>, <4 x half> } %0
510 define { <4 x half>, <4 x half>, <4 x half> } @load_64_3(<4 x half>* %a) #0 {
514 …%0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0v4f16(<4 x …
515   ret { <4 x half>, <4 x half>, <4 x half> } %0
519 define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_64_4(<4 x half>* %a) #0 {
523 …%0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p…
524   ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0
528 define void @store_64_2(<4 x half>* %a, <4 x half> %b, <4 x half> %c) #0 {
532 …tail call void @llvm.aarch64.neon.st1x2.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half>* %a)
537 define void @store_64_3(<4 x half>* %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) #0 {
541 …ll void @llvm.aarch64.neon.st1x3.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x h…
546 define void @store_64_4(<4 x half>* %a, <4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e)…
550 …@llvm.aarch64.neon.st1x4.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e,…
555 define { <8 x half>, <8 x half> } @load_128_2(<8 x half>* %a) #0 {
559   %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x2.v8f16.p0v8f16(<8 x half>* %a)
560   ret { <8 x half>, <8 x half> } %0
564 define { <8 x half>, <8 x half>, <8 x half> } @load_128_3(<8 x half>* %a) #0 {
568 …%0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x3.v8f16.p0v8f16(<8 x …
569   ret { <8 x half>, <8 x half>, <8 x half> } %0
573 define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_128_4(<8 x half>* %a) #0 {
577 …%0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x4.v8f16.p…
578   ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0
582 define void @store_128_2(<8 x half>* %a, <8 x half> %b, <8 x half> %c) #0 {
586 …tail call void @llvm.aarch64.neon.st1x2.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half>* %a)
591 define void @store_128_3(<8 x half>* %a, <8 x half> %b, <8 x half> %c, <8 x half> %d) #0 {
595 …ll void @llvm.aarch64.neon.st1x3.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x h…
600 define void @store_128_4(<8 x half>* %a, <8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e…
604 …@llvm.aarch64.neon.st1x4.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e,…