Home
last modified time | relevance | path

Searched refs:getVGPRClassForBitWidth (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h170 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
H A DSIRegisterInfo.cpp2444 SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const { in getVGPRClassForBitWidth() function in SIRegisterInfo
2684 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass()
2717 RC = getVGPRClassForBitWidth(Size); in getSubRegClass()
2905 return getVGPRClassForBitWidth(std::max(32u, Size)); in getRegClassForSizeOnBank()
3038 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
H A DSIISelLowering.cpp95 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
101 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128)); in SITargetLowering()
104 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160)); in SITargetLowering()
107 addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
110 addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
113 addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224)); in SITargetLowering()
116 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
119 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
125 addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512)); in SITargetLowering()
12119 RC = TRI->getVGPRClassForBitWidth(BitWidth); in getRegForInlineAsmConstraint()
[all …]
H A DSILoadStoreOptimizer.cpp1752 : TRI->getVGPRClassForBitWidth(BitWidth); in getTargetRegisterClass()