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Searched refs:getSchedClassDesc (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/MC/
H A DMCSchedule.cpp58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
78 SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
124 SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DSchedClassResolution.cpp210 SCDesc(STI.getSchedModel().getSchedClassDesc(ResolvedSchedClassId)), in ResolvedSchedClass()
224 while (SchedClassId && SM.getSchedClassDesc(SchedClassId)->isVariant()) { in ResolveVariantSchedClassId()
237 .getSchedClassDesc(SchedClassId) in resolveSchedClassId()
H A DAnalysis.cpp142 SubtargetInfo_->getSchedModel().getSchedClassDesc(SchedClassId); in printInstructionRowCsv()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSchedule.cpp135 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
146 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
344 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); in computeReciprocalThroughput()
H A DMachineCombiner.cpp435 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
H A DMachinePipeliner.cpp1015 STI->getSchedModel().getSchedClassDesc(SchedClass); in minFuncUnits()
1058 STI->getSchedModel().getSchedClassDesc(SchedClass); in calcCriticalResources()
3076 const MCSchedClassDesc *SCDesc = SM.getSchedClassDesc(InsnClass); in canReserveResources()
3116 const MCSchedClassDesc *SCDesc = SM.getSchedClassDesc(InsnClass); in reserveResources()
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp130 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant()) in collectData()
134 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in collectData()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstrBuilder.cpp298 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in populateWrites()
553 bool IsVariant = SM.getSchedClassDesc(SchedClassID)->isVariant(); in createInstrDescImpl()
558 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant()) in createInstrDescImpl()
569 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in createInstrDescImpl()
667 *STI.getSchedModel().getSchedClassDesc(D.SchedClassID); in createInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp87 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldAddSTPToBlock()
H A DAArch64SIMDInstrOpt.cpp230 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldReplaceInst()
242 SCDescRepl = SchedModel.getMCSchedModel()->getSchedClassDesc( in shouldReplaceInst()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSchedule.h346 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc() function
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp508 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in collectWrites()
576 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in checkRAWHazards()
639 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in addRegisterRead()
/llvm-project-15.0.7/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp209 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()