Searched refs:getRegClassConstraint (Results 1 – 8 of 8) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 447 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isBackwardPropagatableRegClassCopy()
468 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
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| H A D | RegisterBankInfo.cpp | 116 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); in getRegBankFromConstraints()
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| H A D | TailDuplicator.cpp | 443 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction()
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| H A D | MachineInstr.cpp | 833 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() function in MachineInstr
904 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect()
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| H A D | TargetInstrInfo.cpp | 815 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); in reassociateOps()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1467 getRegClassConstraint(unsigned OpIdx,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1182 Instr.getRegClassConstraint(OpIdx, TII, TRI); in UpdateOperandRegClass()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 4016 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI); in verifyInstruction()
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