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Searched refs:getOpRegClass (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp678 if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()
827 TII->getOpRegClass(*UseMI, UseMI->getOperandNo(&Use)); in processPHINode()
H A DSIInstrInfo.cpp345 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
1994 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
4246 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
5762 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
5765 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
5768 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
5772 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
5802 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
7064 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { in addUsersToMoveToVALUWorklist()
7216 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); in getDestEquivalentVGPRClass()
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H A DSIInstrInfo.h912 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
938 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
H A DSIInsertWaitcnts.cpp496 const TargetRegisterClass *RC = TII->getOpRegClass(*MI, OpNo); in getRegInterval()
H A DSIRegisterInfo.cpp2240 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()
H A DSIISelLowering.cpp11910 uint32_t DstSize = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddIMGInit()
11915 Register PrevDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()
11926 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()