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Searched refs:getNumRegs (Results 1 – 25 of 109) sorted by relevance

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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits()
28 : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()), in RegisterAliasingTracker()
29 Origins(RegInfo.getNumRegs()) {} in RegisterAliasingTracker()
63 EmptyRegisters(RegInfo.getNumRegs()) {} in RegisterAliasingTrackerCache()
H A DParallelSnippetGenerator.cpp193 BitVector ImplicitUses(State.getRegInfo().getNumRegs()); in generateCodeTemplates()
194 BitVector ImplicitDefs(State.getRegInfo().getNumRegs()); in generateCodeTemplates()
210 BitVector Defs(State.getRegInfo().getNumRegs()); in generateCodeTemplates()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h61 LiveRegs.setUniverse(TRI.getNumRegs()); in LivePhysRegs()
71 LiveRegs.setUniverse(TRI.getNumRegs()); in init()
83 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); in addReg()
93 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); in removeReg()
H A DTargetRegisterInfo.h80 unsigned getNumRegs() const { return MC->getNumRegs(); } in getNumRegs() function
201 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); in getRawAllocationOrder()
355 unsigned NumRegs = getNumRegs(); in getRegisterCosts()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/
H A DRegisterAliasingTest.cpp45 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
52 BitVector sum(RegInfo.getNumRegs()); in TEST_F()
64 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp98 (BestRC->hasSubClass(RC) && RC->getNumRegs() > BestRC->getNumRegs()))) in getMaximalPhysRegClass()
108 for (unsigned i = 0; i < TRC.getNumRegs(); ++i) { in getRegisterOrder()
125 BitVector Reserved(getNumRegs()); in getReservedRegs()
138 for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) { in getReservedRegs()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DRegisterAliasingTest.cpp46 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
51 BitVector sum(RegInfo.getNumRegs()); in TEST_F()
63 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DReachingDefOrUse.h45 BitVector BV = BitVector(this->BC.MRI->getNumRegs(), false); in isReachedBy()
97 BitVector XClobbers = BitVector(this->BC.MRI->getNumRegs(), false); in doesXKillsY()
98 BitVector YClobbers = BitVector(this->BC.MRI->getNumRegs(), false); in doesXKillsY()
133 BitVector Regs = BitVector(this->BC.MRI->getNumRegs(), false); in computeNext()
H A DShrinkWrapping.h68 AllocatorId(AllocId), CalleeSaved(BC.MRI->getNumRegs(), false), in CalleeSavedAnalysis()
69 OffsetsByReg(BC.MRI->getNumRegs(), 0LL), in CalleeSavedAnalysis()
70 HasRestores(BC.MRI->getNumRegs(), false), in CalleeSavedAnalysis()
71 SavingCost(BC.MRI->getNumRegs(), 0ULL), in CalleeSavedAnalysis()
72 SaveFIEByReg(BC.MRI->getNumRegs(), nullptr), in CalleeSavedAnalysis()
73 LoadFIEByReg(BC.MRI->getNumRegs(), nullptr) {} in CalleeSavedAnalysis()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp45 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
46 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker()
52 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { in StartBlock()
114 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
274 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { in ScanInstruction()
473 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { in BreakAntiDependencies()
527 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0); in BreakAntiDependencies()
H A DRegisterClassInfo.cpp63 CalleeSavedAliases.assign(TRI->getNumRegs(), 0); in runOnMachineFunction()
74 BitVector CSRHintsForAllocOrder(TRI->getNumRegs()); in runOnMachineFunction()
111 unsigned NumRegs = RC->getNumRegs(); in compute()
213 unsigned NReserved = RC->getNumRegs() - NAllocatableRegs; in computePSetLimit()
H A DRegUsageInfoCollector.cpp127 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs()); in runOnMachineFunction()
154 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction()
181 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction()
H A DRDFRegisters.cpp30 RegInfos.resize(TRI.getNumRegs()); in PhysicalRegisterInfo()
32 BitVector BadRC(TRI.getNumRegs()); in PhysicalRegisterInfo()
87 for (unsigned I = 1, E = TRI.getNumRegs(); I != E; ++I) { in PhysicalRegisterInfo()
98 BitVector AS(TRI.getNumRegs()); in PhysicalRegisterInfo()
113 for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) { in getAliasSet()
204 unsigned NumRegs = TRI.getNumRegs(); in aliasMM()
H A DTargetFrameLoweringImpl.cpp73 CalleeSaves.resize(TRI.getNumRegs()); in getCalleeSaves()
91 SavedRegs.resize(TRI.getNumRegs()); in determineCalleeSaves()
H A DMachineRegisterInfo.cpp46 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); in MachineRegisterInfo()
76 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
257 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) in verifyUseLists()
505 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && in freezeReservedRegs()
597 assert(Reg && (Reg < TRI->getNumRegs()) && in disableCalleeSavedRegister()
H A DTargetRegisterInfo.cpp89 BitVector Checked(getNumRegs()); in checkAllSuperRegsMarked()
127 else if (Reg < TRI->getNumRegs()) { in printReg()
258 BitVector Allocatable(getNumRegs()); in getAllocatableSet()
494 unsigned N = (getNumRegs()+31) / 32; in regmaskSubsetEqual()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegAnalysis.cpp115 BitVector BV(BC.MRI->getNumRegs(), false); in beConservative()
132 BitVector BV(BC.MRI->getNumRegs(), false); in isConservative()
197 BitVector UsedRegs = BitVector(BC.MRI->getNumRegs(), false); in getFunctionUsedRegsList()
216 BitVector RegsKilled = BitVector(BC.MRI->getNumRegs(), false); in getFunctionClobberList()
H A DRegReAssign.cpp361 GPRegs = BitVector(BC.MRI->getNumRegs(), false); in setupAggressivePass()
368 ClassicRegs = BitVector(BC.MRI->getNumRegs(), false); in setupConservativePass()
369 CalleeSaved = BitVector(BC.MRI->getNumRegs(), false); in setupConservativePass()
370 ClassicCSR = BitVector(BC.MRI->getNumRegs(), false); in setupConservativePass()
371 ExtendedCSR = BitVector(BC.MRI->getNumRegs(), false); in setupConservativePass()
400 RegScore = std::vector<int64_t>(BC.MRI->getNumRegs(), 0); in runOnFunctions()
401 RankedRegs = std::vector<size_t>(BC.MRI->getNumRegs(), 0); in runOnFunctions()
H A DStackAvailableExpressions.cpp95 BitVector XClobbers = BitVector(BC.MRI->getNumRegs(), false); in doesXKillsY()
96 BitVector YClobbers = BitVector(BC.MRI->getNumRegs(), false); in doesXKillsY()
H A DShrinkWrapping.cpp45 BitVector BlacklistedRegs(BC.MRI->getNumRegs(), false); in analyzeSaves()
727 UsesByReg = std::vector<BitVector>(BC.MRI->getNumRegs(), in classifyCSRUses()
735 BitVector BV = BitVector(BC.MRI->getNumRegs(), false); in classifyCSRUses()
756 for (unsigned I = 0, E = BC.MRI->getNumRegs(); I != E; ++I) { in pruneUnwantedCSRs()
838 for (unsigned I = 0, E = BC.MRI->getNumRegs(); I != E; ++I) { in computeSaveLocations()
860 DomOrder = std::vector<MCPhysReg>(BC.MRI->getNumRegs(), 0); in computeDomOrder()
862 for (MCPhysReg I = 0, E = BC.MRI->getNumRegs(); I != E; ++I) { in computeDomOrder()
886 for (MCPhysReg I = 0, E = BC.MRI->getNumRegs(); I != E; ++I) in computeDomOrder()
1213 BitVector BV = BitVector(BC.MRI->getNumRegs(), false); in doesInstUsesCSR()
1283 for (unsigned I = 0, E = BC.MRI->getNumRegs(); I != E; ++I) { in moveSaveRestores()
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H A DStokeInfo.cpp155 LLVM_DEBUG(dbgs() << "\tgetNumRegs " << BC.MRI->getNumRegs() << "\n"); in runOnFunctions()
160 NumRegs = BC.MRI->getNumRegs(); in runOnFunctions()
/llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/
H A DReduceRegisterMasks.cpp25 const unsigned NumRegs = TRI->getNumRegs(); in reduceMasksInFunction()
40 MachineOperand::getRegMaskSize(TRI->getNumRegs()); in reduceMasksInFunction()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCRegisterInfo.cpp46 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
120 report_fatal_error("unknown codeview register " + (RegNum < getNumRegs() in getCodeViewRegNum()
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp463 for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) { in initAliases()
464 BitVector BV(RegInfo->getNumRegs(), false); in initAliases()
471 for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I != E; ++I) { in initAliases()
478 for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I) in initAliases()
491 for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) { in initAliases()
511 SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs()); in getRegSize()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.cpp25 return BitVector(getNumRegs()); in getReservedRegs()

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