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Searched refs:getNumRegClasses (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterBank.cpp34 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify()
100 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print()
104 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print()
H A DRegisterClassInfo.cpp51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
H A DRegAllocFast.cpp1083 assert(RegClassDefCounts.size() == TRI->getNumRegClasses()); in addRegClassDefCounts()
1087 for (unsigned RCIdx = 0, RCIdxEnd = TRI->getNumRegClasses(); in addRegClassDefCounts()
1098 for (unsigned RCIdx = 0, RCIdxEnd = TRI->getNumRegClasses(); in addRegClassDefCounts()
1190 std::vector<unsigned> RegClassDefCounts(TRI->getNumRegClasses(), 0); in allocateInstruction()
H A DTargetRegisterInfo.cpp282 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) in firstCommonClass()
H A DTargetLoweringBase.cpp1257 BitVector SuperRegRC(TRI->getNumRegClasses()); in findRepresentativeClass()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h733 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
744 unsigned getNumRegClasses() const { in getNumRegClasses() function
751 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
1153 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1252 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) { in BitMaskClassIterator()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h537 unsigned getNumRegClasses() const { in getNumRegClasses() function
544 assert(i < getNumRegClasses() && "Register Class ID out of range"); in getRegClass()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp54 unsigned NumRC = TRI->getNumRegClasses(); in ResourcePriorityQueue()
H A DScheduleDAGRRList.cpp1775 unsigned NumRC = TRI->getNumRegClasses(); in RegReductionPQBase()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp1717 for (unsigned i=0; i< TRI->getNumRegClasses(); i++) { in setAndEmitFunctionVirtualRegisters()
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp277 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) { in initNames2RegClasses()