Home
last modified time | relevance | path

Searched refs:getNumDefs (Results 1 – 25 of 73) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp98 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
138 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init()
195 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
537 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
554 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
574 for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J) in registerProducer()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp239 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
H A DBreakFalseDeps.cpp195 for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) { in processDefs()
217 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
H A DPeepholeOptimizer.cpp890 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1190 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1337 if (MCID.getNumDefs() != 1) in isLoadFoldable()
1358 if (MCID.getNumDefs() != 1) in isMoveImmediate()
1531 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1771 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands(); in runOnMachineFunction()
1852 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2068 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
H A DImplicitNullChecks.cpp371 if (MI.getDesc().getNumDefs() > 1) in isSuitableMemoryOp()
715 unsigned NumDefs = MI->getDesc().getNumDefs(); in insertFaultingInstr()
H A DDetectDeadLanes.cpp275 if (MI.getDesc().getNumDefs() != 1) in transferDefinedLanesStep()
423 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1931 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1933 if (II.getNumDefs() >= 1) in fastEmitInst_r()
1952 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1955 if (II.getNumDefs() >= 1) in fastEmitInst_rr()
1975 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1979 if (II.getNumDefs() >= 1) in fastEmitInst_rrr()
2003 if (II.getNumDefs() >= 1) in fastEmitInst_ri()
2025 if (II.getNumDefs() >= 1) in fastEmitInst_rii()
2048 if (II.getNumDefs() >= 1) in fastEmitInst_f()
2069 if (II.getNumDefs() >= 1) in fastEmitInst_rri()
[all …]
H A DScheduleDAGSDNodes.cpp127 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg)) in CheckForPhysRegDependency()
468 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
569 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
656 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
H A DScheduleDAGRRList.cpp1285 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1431 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) in DelayForLiveRegsBottomUp()
2130 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2176 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2305 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2322 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2836 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2893 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
3081 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
H A DInstrEmitter.cpp133 if (i+II.getNumDefs() < II.getNumOperands()) { in EmitCopyFromReg()
135 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
198 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs(); in CreateVirtualRegisters()
964 unsigned NumDefs = II.getNumDefs(); in EmitMachineNode()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h144 unsigned getNumDefs() const { return getNumOperands() - 1; } in getNumDefs() function
146 Register getSourceReg() const { return getOperand(getNumDefs()).getReg(); } in getSourceReg()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp66 if (MCDesc.getNumDefs() == 1 && MCDesc.getNumOperands() >= 2) { in hasType()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstrBuilder.cpp268 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in verifyOperands()
343 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in populateWrites()
466 unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs(); in populateReads()
475 for (unsigned I = 0, OpIndex = MCDesc.getNumDefs(); I < NumExplicitUses; in populateReads()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp300 else if (OpNo >= Desc.getNumDefs() && !IsVariadicDef) in printOperand()
307 if (OpNo < MII.get(MI->getOpcode()).getNumDefs() || IsVariadicDef) in printOperand()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVDuplicatesTracker.cpp52 for (auto i = MI->getNumDefs(); i < MI->getNumOperands(); i++) { in buildDepsGraph()
H A DSPIRVInstrInfo.cpp51 if (MI.getNumDefs() >= 1 && MI.getOperand(0).isReg()) { in isTypeDeclInstr()
H A DSPIRVModuleAnalysis.cpp195 if (NumAOps != B->getNumOperands() || A.getNumDefs() != B->getNumDefs()) in findSameInstrInMS()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/AsmParser/
H A DWebAssemblyAsmTypeCheck.cpp333 for (unsigned I = II.getNumOperands(); I > II.getNumDefs(); I--) { in typeCheck()
342 for (unsigned I = 0; I < II.getNumDefs(); I++) { in typeCheck()
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp339 for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) { in getClobberedRegs()
376 for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) { in getWrittenRegs()
426 for (unsigned I = InstInfo.getNumDefs(), E = InstInfo.getNumOperands(); in getSrcRegs()
/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DLivenessAnalysis.h140 if (!Point.getOperand(I).isReg() || I < InstInfo.getNumDefs()) in computeNext()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp90 assert(MI.getDesc().getNumDefs() == 1 && in localizeInterBlock()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp142 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { in processMachineBasicBlock()
H A DAArch64FastISel.cpp1309 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1310 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1395 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1396 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1439 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
2118 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
2353 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitCompareAndBranch()
2484 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2502 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs()); in selectIndirectBr()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h245 unsigned getNumDefs() const { return NumDefs; } in getNumDefs() function
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DStackMaps.h174 NumDefs = MI->getNumDefs(); in StatepointOpers()

123