| /llvm-project-15.0.7/llvm/unittests/MC/AMDGPU/ |
| H A D | DwarfRegMappings.cpp | 55 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); in TEST()
73 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); in TEST()
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| /llvm-project-15.0.7/llvm/unittests/Target/AMDGPU/ |
| H A D | DwarfRegMappings.cpp | 60 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); in TEST()
83 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); in TEST()
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| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum, in getLLVMRegNum() function in MCRegisterInfo
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) in getDwarfRegNumFromDwarfEHRegNum()
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| H A D | MCAsmStreamer.cpp | 1854 if (Optional<unsigned> LLVMRegister = MRI->getLLVMRegNum(Register, true)) { in EmitRegisterName()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 586 getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true)); in generateCompactUnwindEncoding()
609 unsigned LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true); in generateCompactUnwindEncoding()
610 unsigned FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true); in generateCompactUnwindEncoding()
632 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding()
643 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding()
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| /llvm-project-15.0.7/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFExpression.cpp | 246 if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(DwarfRegNum, isEH)) { in prettyPrintRegisterOp()
418 Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false); in printCompactDWARFExpr()
430 Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false); in printCompactDWARFExpr()
467 Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false); in printCompactDWARFExpr()
478 Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false); in printCompactDWARFExpr()
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| H A D | DWARFDebugFrame.cpp | 35 if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(RegNum, IsEH)) { in printRegister()
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| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | RegReAssign.cpp | 81 const MCPhysReg Reg2 = *BC.MRI->getLLVMRegNum(CFIReg2, /*isEH=*/false); in swap()
118 const MCPhysReg Reg = *BC.MRI->getLLVMRegNum(CFIReg, /*isEH=*/false); in swap()
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| H A D | FrameAnalysis.cpp | 158 *BC.MRI->getLLVMRegNum(CfaReg, /*isEH=*/false)) { in decodeFrameAccess()
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| H A D | ShrinkWrapping.cpp | 372 const uint16_t Reg = *BC.MRI->getLLVMRegNum(CfaReg, /*isEH=*/false); in classifyCFIs()
402 BC.MRI->getLLVMRegNum(CFI->getRegister(), in classifyCFIs()
408 BC.MRI->getLLVMRegNum(CFI->getRegister(), in classifyCFIs()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackend.cpp | 1131 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding()
1137 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding()
1140 Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 1392 if (*MRI.getLLVMRegNum(Inst.getRegister(), true) != in generateCompactUnwindEncoding()
1440 unsigned Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding()
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| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 517 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | StackMaps.cpp | 250 unsigned LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false); in parseOperand()
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| H A D | MachineOperand.cpp | 448 if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true)) in printCFIRegister()
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