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Searched refs:getCondCode (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/bolt/lib/Passes/
H A DThreeWayBranch.cpp80 unsigned FirstCC = BC.MIB->getCondCode(*FirstJump); in runOnFunction()
87 BC.MIB->getInvertedCondCode(BC.MIB->getCondCode(*SecondJump)), in runOnFunction()
93 BC.MIB->getCondCode(*SecondJump), FirstCC)); in runOnFunction()
H A DCMOVConversion.cpp213 unsigned CC = BC.MIB->getCondCode(*BranchInstrIter); in runOnFunction()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp747 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
757 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
837 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
843 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
871 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
879 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
911 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
937 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
H A DSIISelLowering.cpp4898 DAG.getCondCode(CCOpcode)); in lowerICMPIntrinsic()
4928 Src1, DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic()
4968 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h793 SDValue getCondCode(ISD::CondCode Cond);
1092 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1093 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1104 return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask,
1123 False, getCondCode(Cond));
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp940 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
1025 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1047 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC()
1050 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC()
1882 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1967 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
H A DLegalizeIntegerTypes.cpp4830 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
4888 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
4917 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
4936 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
4953 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
H A DLegalizeDAG.cpp3610 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3755 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3787 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
H A DTargetLowering.cpp9725 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
9738 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
H A DSelectionDAG.cpp1839 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
H A DSelectionDAGBuilder.cpp7355 Opers.push_back(DAG.getCondCode(Condition)); in visitConstrainedFPIntrinsic()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp103 unsigned getCondCode(const MCInst &Inst) const override { in getCondCode() function in __anoncef8f4420111::X86MCPlusBuilder
667 X86::CondCode CC = static_cast<X86::CondCode>(getCondCode(SecondInst)); in isMacroOpFusionPair()
2002 getCondCode(*I) == X86::COND_INVALID) { in analyzeBranch()
2943 unsigned InvCC = getInvertedCondCode(getCondCode(Inst)); in reverseBranchCondition()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp954 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon2aa686d00111::ARMOperand
2429 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL()
2436 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI()
2443 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS()
2451 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU()
2458 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP()
2485 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2486 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2537 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
3907 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
[all …]
/llvm-project-15.0.7/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp787 unsigned getCondCode(const MCInst &Inst) const override { in getCondCode() function in __anon77c122c80111::AArch64MCPlusBuilder
/llvm-project-15.0.7/bolt/include/bolt/Core/
H A DMCPlusBuilder.h1622 virtual unsigned getCondCode(const MCInst &Inst) const { in getCondCode() function
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3932 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerSELECT()
3941 SDValue SetNE = DAG.getCondCode(ISD::SETNE); in lowerSELECT()
3961 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerBRCOND()
3968 DAG.getCondCode(ISD::SETNE), Op.getOperand(2)); in lowerBRCOND()
4325 DAG.getCondCode(ISD::SETNE), Mask, VL); in lowerVectorMaskTruncLike()
4949 DAG.getCondCode(ISD::SETEQ), Mask, VL); in LowerINTRINSIC_WO_CHAIN()
6432 DAG.getCondCode(ISD::SETNE), Mask, VL); in lowerVPFPIntConvOp()
8772 CC = DAG.getCondCode(CCVal); in combine_CC()
8793 CC = DAG.getCondCode(CCVal); in combine_CC()
8811 CC = DAG.getCondCode(CCVal); in combine_CC()
/llvm-project-15.0.7/bolt/lib/Core/
H A DBinaryFunction.cpp3537 if (BC.MIB->getCanonicalBranchCondCode(BC.MIB->getCondCode( in dfs()
3538 *CondBranch)) == BC.MIB->getCondCode(*CondBranch)) { in dfs()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp589 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anone48315620111::AArch64Operand
1715 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
2260 OS << "<condcode " << getCondCode() << ">"; in print()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16298 N->getOperand(2), Splat, DAG.getCondCode(CC)); in tryConvertSVEWideCompare()
16663 N->getOperand(3), DAG.getCondCode(ISD::SETUGE)); in performIntrinsicCombine()
16669 N->getOperand(3), DAG.getCondCode(ISD::SETUGT)); in performIntrinsicCombine()
16675 N->getOperand(3), DAG.getCondCode(ISD::SETGE)); in performIntrinsicCombine()
16681 N->getOperand(3), DAG.getCondCode(ISD::SETGT)); in performIntrinsicCombine()
16687 N->getOperand(3), DAG.getCondCode(ISD::SETEQ)); in performIntrinsicCombine()
16693 N->getOperand(3), DAG.getCondCode(ISD::SETNE)); in performIntrinsicCombine()
16698 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performIntrinsicCombine()
18686 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine()
21033 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)}); in convertFixedMaskToScalableVector()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6720 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC()
9157 DAG.getCondCode(ISD::SETNE)); in LowerTruncatei1()
10302 DAG.getCondCode(CC)); in LowerFSETCC()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3519 DAG.getCondCode(CC)); in LowerSETCC()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24144 SDValue CC = DAG.getCondCode(Cond); in splitIntVSETCC()