Home
last modified time | relevance | path

Searched refs:flw (Results 1 – 25 of 64) sorted by relevance

123

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dcallee-saved-fpr32s.ll32 ; ILP32-NEXT: flw ft4, 16(a1)
33 ; ILP32-NEXT: flw ft5, 20(a1)
34 ; ILP32-NEXT: flw ft6, 24(a1)
35 ; ILP32-NEXT: flw ft7, 28(a1)
36 ; ILP32-NEXT: flw fa0, 32(a1)
37 ; ILP32-NEXT: flw fa1, 36(a1)
38 ; ILP32-NEXT: flw fa2, 40(a1)
39 ; ILP32-NEXT: flw fa3, 44(a1)
40 ; ILP32-NEXT: flw fa4, 48(a1)
41 ; ILP32-NEXT: flw fa5, 52(a1)
[all …]
H A Dfastcc-float.ll26 ; CHECK-NEXT: flw ft0, 64(sp)
27 ; CHECK-NEXT: flw ft1, 68(sp)
28 ; CHECK-NEXT: flw ft2, 72(sp)
29 ; CHECK-NEXT: flw ft3, 76(sp)
30 ; CHECK-NEXT: flw ft4, 80(sp)
31 ; CHECK-NEXT: flw ft5, 84(sp)
32 ; CHECK-NEXT: flw ft6, 88(sp)
33 ; CHECK-NEXT: flw ft7, 92(sp)
34 ; CHECK-NEXT: flw ft8, 96(sp)
35 ; CHECK-NEXT: flw ft9, 100(sp)
[all …]
H A Dcalling-conv-ilp32f-ilp32d-common.ll29 ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
59 ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
99 ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI5_0)(a0)
101 ; RV32-ILP32FD-NEXT: flw fa1, %lo(.LCPI5_1)(a0)
103 ; RV32-ILP32FD-NEXT: flw fa2, %lo(.LCPI5_2)(a0)
105 ; RV32-ILP32FD-NEXT: flw fa3, %lo(.LCPI5_3)(a0)
107 ; RV32-ILP32FD-NEXT: flw fa4, %lo(.LCPI5_4)(a0)
109 ; RV32-ILP32FD-NEXT: flw fa5, %lo(.LCPI5_5)(a0)
111 ; RV32-ILP32FD-NEXT: flw fa6, %lo(.LCPI5_6)(a0)
113 ; RV32-ILP32FD-NEXT: flw fa7, %lo(.LCPI5_7)(a0)
[all …]
H A Dinterrupt-attr-nocall.ll217 ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
219 ; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
224 ; CHECK-RV32IF-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
225 ; CHECK-RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
236 ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
238 ; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
316 ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
318 ; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
340 ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
342 ; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
[all …]
H A Dinterrupt-attr.ll168 ; CHECK-RV32-F-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload
169 ; CHECK-RV32-F-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
170 ; CHECK-RV32-F-NEXT: flw fa1, 88(sp) # 4-byte Folded Reload
171 ; CHECK-RV32-F-NEXT: flw fa2, 84(sp) # 4-byte Folded Reload
172 ; CHECK-RV32-F-NEXT: flw fa3, 80(sp) # 4-byte Folded Reload
173 ; CHECK-RV32-F-NEXT: flw fa4, 76(sp) # 4-byte Folded Reload
174 ; CHECK-RV32-F-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
175 ; CHECK-RV32-F-NEXT: flw fa6, 68(sp) # 4-byte Folded Reload
176 ; CHECK-RV32-F-NEXT: flw fa7, 64(sp) # 4-byte Folded Reload
177 ; CHECK-RV32-F-NEXT: flw ft8, 60(sp) # 4-byte Folded Reload
[all …]
H A Dfloat-mem.ll7 define dso_local float @flw(float *%a) nounwind {
8 ; CHECKIF-LABEL: flw:
10 ; CHECKIF-NEXT: flw ft0, 0(a0)
11 ; CHECKIF-NEXT: flw ft1, 12(a0)
49 ; CHECKIF-NEXT: flw ft0, %lo(G)(a0)
52 ; CHECKIF-NEXT: flw ft0, 36(a1)
69 ; RV32IF-NEXT: flw ft0, -273(a0)
78 ; RV64IF-NEXT: flw ft0, -273(a0)
100 ; RV32IF-NEXT: flw ft0, 4(sp)
103 ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
[all …]
H A Dinline-asm-f-abi-names.ll349 ; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
361 ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
378 ; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
390 ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
407 ; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
419 ; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
436 ; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
448 ; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
781 ; RV32IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload
793 ; RV64IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload
[all …]
H A Dghccc-rv32.ll48 ; CHECK-NEXT: flw fs5, %lo(f6)(a0)
50 ; CHECK-NEXT: flw fs4, %lo(f5)(a0)
52 ; CHECK-NEXT: flw fs3, %lo(f4)(a0)
54 ; CHECK-NEXT: flw fs2, %lo(f3)(a0)
56 ; CHECK-NEXT: flw fs1, %lo(f2)(a0)
58 ; CHECK-NEXT: flw fs0, %lo(f1)(a0)
H A Dghccc-rv64.ll48 ; CHECK-NEXT: flw fs5, %lo(f6)(a0)
50 ; CHECK-NEXT: flw fs4, %lo(f5)(a0)
52 ; CHECK-NEXT: flw fs3, %lo(f4)(a0)
54 ; CHECK-NEXT: flw fs2, %lo(f3)(a0)
56 ; CHECK-NEXT: flw fs1, %lo(f2)(a0)
58 ; CHECK-NEXT: flw fs0, %lo(f1)(a0)
H A Dinline-asm-f-constraint-f.ll18 ; RV32F-NEXT: flw ft0, %lo(gf)(a1)
29 ; RV64F-NEXT: flw ft0, %lo(gf)(a1)
45 ; RV32F-NEXT: flw fs0, %lo(gf)(a1)
56 ; RV64F-NEXT: flw fs0, %lo(gf)(a1)
H A Dfloat-round-conv-sat.ll30 ; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
40 ; RV32IF-NEXT: flw ft0, %lo(.LCPI1_1)(a0)
123 ; RV32IF-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
185 ; RV32IF-NEXT: flw ft0, %lo(.LCPI5_0)(a0)
195 ; RV32IF-NEXT: flw ft0, %lo(.LCPI5_1)(a0)
278 ; RV32IF-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
340 ; RV32IF-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
350 ; RV32IF-NEXT: flw ft0, %lo(.LCPI9_1)(a0)
433 ; RV32IF-NEXT: flw ft0, %lo(.LCPI11_0)(a0)
495 ; RV32IF-NEXT: flw ft0, %lo(.LCPI13_0)(a0)
[all …]
H A Dhalf-round-conv-sat.ll31 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
43 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI1_1)(a0)
129 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
192 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI5_0)(a0)
204 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI5_1)(a0)
290 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
353 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
365 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI9_1)(a0)
451 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI11_0)(a0)
514 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI13_0)(a0)
[all …]
H A Dfloat-imm.ll12 ; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
21 ; CHECK-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
H A Dcalling-conv-half.ll183 ; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
196 ; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
208 ; RV64-LP64F-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
220 ; RV32-ILP32ZFHMIN-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
232 ; RV64-LP64ZFHMIN-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
455 ; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
474 ; RV64-LP64F-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
512 ; RV64-LP64ZFHMIN-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
551 ; RV64IF-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
558 ; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dcompress-rv32f.s13 flw ft0, 124(sp) label
15 # CHECK-ALIAS: flw ft0, 124(sp)
23 flw fs0, 124(s0) label
25 # CHECK-ALIAS: flw fs0, 124(s0)
26 # CHECK-INST: c.flw fs0, 124(s0)
H A Drv32f-valid.s12 # CHECK-ASM-AND-OBJ: flw ft0, 12(a0)
14 flw f0, 12(a0) label
15 # CHECK-ASM-AND-OBJ: flw ft1, 4(ra)
17 flw f1, +4(ra) label
18 # CHECK-ASM-AND-OBJ: flw ft2, -2048(a3)
20 flw f2, -2048(x13) label
23 flw f3, %lo(2048)(s1) label
24 # CHECK-ASM-AND-OBJ: flw ft4, 2047(s2)
26 flw f4, 2047(s2) label
27 # CHECK-ASM-AND-OBJ: flw ft5, 0(s3)
[all …]
H A Drv32f-invalid.s5 flw ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tpre… label
9 flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction label
13 flw ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction label
14 flw ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register label
H A Drvf-pseudos.s6 # CHECK: flw fa2, %pcrel_lo(.Lpcrel_hi0)(a2)
7 flw fa2, a_symbol, a2 label
H A Drv32fc-aliases-valid.s7 # CHECK-EXPAND: c.flw fs0, 0(s1)
8 c.flw f8, (x9)
H A Drv32fc-invalid.s4 c.flw ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
11 c.flw fs0, -4(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 4 bytes in the ra…
H A Drvf-aliases-valid.s26 # CHECK-INST: flw ft0, 0(a0)
27 # CHECK-ALIAS: flw ft0, 0(a0)
28 flw f0, (a0) label
113 # CHECK-INST: flw ft0, 0(a0)
114 # CHECK-ALIAS: flw ft0, 0(a0)
115 flw f0, (x10) label
H A Dinvalid-instruction-spellcheck.s20 # CHECK-RV32IF: did you mean: flw, la, lb, lh, li, lw
22 # CHECK-RV64IF: did you mean: flw, la, lb, ld, lh, li, lw
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfround-sdnode.ll137 ; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
139 ; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0)
158 ; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
160 ; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0)
179 ; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
181 ; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0)
200 ; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
202 ; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0)
221 ; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
223 ; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0)
H A Dfptosi-sat.ll21 ; CHECK32-NEXT: flw ft0, %lo(.LCPI0_0)(a0)
26 ; CHECK32-NEXT: flw ft0, %lo(.LCPI0_1)(a0)
41 ; CHECK64-NEXT: flw ft0, %lo(.LCPI0_0)(a0)
47 ; CHECK64-NEXT: flw ft0, %lo(.LCPI0_1)(a0)
67 ; CHECK32-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
72 ; CHECK32-NEXT: flw ft0, %lo(.LCPI1_1)(a0)
87 ; CHECK64-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
159 ; CHECK-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
161 ; CHECK-NEXT: flw ft1, %lo(.LCPI3_1)(a0)
180 ; CHECK-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
[all …]
H A Dffloor-sdnode.ll152 ; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
155 ; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0)
175 ; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
178 ; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0)
198 ; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
201 ; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0)
221 ; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
224 ; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0)
244 ; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
247 ; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0)

123