Home
last modified time | relevance | path

Searched refs:fcvt (Results 1 – 25 of 161) sorted by relevance

1234567

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dvecreduce-fmax-legalization.ll55 ; CHECK-NOFP-NEXT: fcvt s2, h0
56 ; CHECK-NOFP-NEXT: fcvt s1, h1
60 ; CHECK-NOFP-NEXT: fcvt h1, s1
61 ; CHECK-NOFP-NEXT: fcvt s2, h2
62 ; CHECK-NOFP-NEXT: fcvt s0, h0
63 ; CHECK-NOFP-NEXT: fcvt s1, h1
65 ; CHECK-NOFP-NEXT: fcvt h1, s1
66 ; CHECK-NOFP-NEXT: fcvt s1, h1
68 ; CHECK-NOFP-NEXT: fcvt h0, s0
84 ; CHECK-NOFP-NEXT: fcvt s2, h0
[all …]
H A Dvecreduce-fmin-legalization.ll55 ; CHECK-NOFP-NEXT: fcvt s2, h0
56 ; CHECK-NOFP-NEXT: fcvt s1, h1
60 ; CHECK-NOFP-NEXT: fcvt h1, s1
61 ; CHECK-NOFP-NEXT: fcvt s2, h2
62 ; CHECK-NOFP-NEXT: fcvt s0, h0
63 ; CHECK-NOFP-NEXT: fcvt s1, h1
65 ; CHECK-NOFP-NEXT: fcvt h1, s1
66 ; CHECK-NOFP-NEXT: fcvt s1, h1
68 ; CHECK-NOFP-NEXT: fcvt h0, s0
84 ; CHECK-NOFP-NEXT: fcvt s2, h0
[all …]
H A Dvecreduce-fadd.ll25 ; CHECKNOFP16-NEXT: fcvt s2, h0
26 ; CHECKNOFP16-NEXT: fcvt s1, h1
30 ; CHECKNOFP16-NEXT: fcvt h1, s1
31 ; CHECKNOFP16-NEXT: fcvt s2, h2
32 ; CHECKNOFP16-NEXT: fcvt s0, h0
33 ; CHECKNOFP16-NEXT: fcvt s1, h1
35 ; CHECKNOFP16-NEXT: fcvt h1, s1
36 ; CHECKNOFP16-NEXT: fcvt s1, h1
38 ; CHECKNOFP16-NEXT: fcvt h0, s0
56 ; CHECKNOFP16-NEXT: fcvt s2, h0
[all …]
H A Dfaddp-half.ll110 ; CHECKNOFP16-NEXT: fcvt s0, h0
111 ; CHECKNOFP16-NEXT: fcvt s1, h1
113 ; CHECKNOFP16-NEXT: fcvt h0, s0
131 ; CHECKNOFP16-NEXT: fcvt s0, h0
132 ; CHECKNOFP16-NEXT: fcvt s1, h1
134 ; CHECKNOFP16-NEXT: fcvt h0, s0
154 ; CHECKNOFP16-NEXT: fcvt s4, h0
158 ; CHECKNOFP16-NEXT: fcvt s1, h1
159 ; CHECKNOFP16-NEXT: fcvt s5, h2
162 ; CHECKNOFP16-NEXT: fcvt s3, h3
[all …]
H A Dfp16-v8-instructions.ll10 ; CHECK-CVT-NEXT: fcvt s4, h1
11 ; CHECK-CVT-NEXT: fcvt s5, h0
16 ; CHECK-CVT-NEXT: fcvt s2, h2
17 ; CHECK-CVT-NEXT: fcvt s3, h3
19 ; CHECK-CVT-NEXT: fcvt s5, h6
20 ; CHECK-CVT-NEXT: fcvt s6, h7
21 ; CHECK-CVT-NEXT: fcvt s7, h16
24 ; CHECK-CVT-NEXT: fcvt h2, s4
29 ; CHECK-CVT-NEXT: fcvt h3, s3
31 ; CHECK-CVT-NEXT: fcvt h7, s7
[all …]
H A Dvector-fcopysign.ll194 ; NOFP16-NEXT: fcvt s5, h1
195 ; NOFP16-NEXT: fcvt s6, h0
200 ; NOFP16-NEXT: fcvt s3, h3
201 ; NOFP16-NEXT: fcvt s4, h4
203 ; NOFP16-NEXT: fcvt s6, h7
205 ; NOFP16-NEXT: fcvt s1, h1
208 ; NOFP16-NEXT: fcvt h0, s5
311 ; FP16-NEXT: fcvt h1, d1
312 ; FP16-NEXT: fcvt h3, d3
314 ; FP16-NEXT: fcvt h3, d2
[all …]
H A Df16-instructions.ll19 ; CHECK-CVT-NEXT: fcvt s1, h1
20 ; CHECK-CVT-NEXT: fcvt s0, h0
22 ; CHECK-CVT-NEXT: fcvt h0, s0
35 ; CHECK-CVT-NEXT: fcvt s1, h1
36 ; CHECK-CVT-NEXT: fcvt s0, h0
38 ; CHECK-CVT-NEXT: fcvt h0, s0
51 ; CHECK-CVT-NEXT: fcvt s1, h1
52 ; CHECK-CVT-NEXT: fcvt s0, h0
54 ; CHECK-CVT-NEXT: fcvt h0, s0
849 ; GISEL-NEXT: fcvt s0, h0
[all …]
H A Dfp-intrinsics-fp16.ll86 ; CHECK-NEXT: fcvt s1, h1
87 ; CHECK-NEXT: fcvt s0, h0
89 ; CHECK-NEXT: fcvt h0, s0
302 ; CHECK-NEXT: fcvt s0, h0
304 ; CHECK-NEXT: fcvt h0, s0
317 ; CHECK-NEXT: fcvt s0, h0
319 ; CHECK-NEXT: fcvt h0, s0
332 ; CHECK-NEXT: fcvt s0, h0
334 ; CHECK-NEXT: fcvt h0, s0
347 ; CHECK-NEXT: fcvt s1, h1
[all …]
H A Df16-convert.ll6 ; CHECK-NEXT: fcvt s0, [[HREG]]
125 ; CHECK-NEXT: fcvt h0, s0
136 ; CHECK-NEXT: fcvt s0, d0
137 ; CHECK-NEXT: fcvt h0, s0
149 ; CHECK-NEXT: fcvt h0, s0
162 ; CHECK-NEXT: fcvt s0, d0
163 ; CHECK-NEXT: fcvt h0, s0
177 ; CHECK-NEXT: fcvt h0, s0
189 ; CHECK-NEXT: fcvt s0, d0
190 ; CHECK-NEXT: fcvt h0, s0
[all …]
H A Dfcvt-fixed.ll91 ; CHECK-NO16-NEXT: fcvt s0, h0
93 ; CHECK-NO16-NEXT: fcvt h0, s0
94 ; CHECK-NO16-NEXT: fcvt s0, h0
111 ; CHECK-NO16-NEXT: fcvt s0, h0
113 ; CHECK-NO16-NEXT: fcvt h0, s0
114 ; CHECK-NO16-NEXT: fcvt s0, h0
131 ; CHECK-NO16-NEXT: fcvt s0, h0
133 ; CHECK-NO16-NEXT: fcvt h0, s0
134 ; CHECK-NO16-NEXT: fcvt s0, h0
151 ; CHECK-NO16-NEXT: fcvt s0, h0
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv64zdinx-valid.s10 # CHECK-ASM-AND-OBJ: fcvt.l.d a0, t0, dyn
13 fcvt.l.d a0, t0, dyn
14 # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, t1, dyn
17 fcvt.lu.d a1, t1, dyn
18 # CHECK-ASM-AND-OBJ: fcvt.d.l t3, a3, dyn
21 fcvt.d.l t3, a3, dyn
25 fcvt.d.lu t4, a4, dyn
31 fcvt.d.l t3, a3, rne
35 fcvt.d.lu t4, a4, rtz
39 fcvt.l.d a0, t0, rdn
[all …]
H A Drv64f-valid.s10 # CHECK-ASM-AND-OBJ: fcvt.l.s a0, ft0, dyn
13 fcvt.l.s a0, ft0, dyn
14 # CHECK-ASM-AND-OBJ: fcvt.lu.s a1, ft1, dyn
17 fcvt.lu.s a1, ft1, dyn
18 # CHECK-ASM-AND-OBJ: fcvt.s.l ft2, a2, dyn
21 fcvt.s.l ft2, a2, dyn
25 fcvt.s.lu ft3, a3, dyn
30 fcvt.l.s a4, ft4, rne
33 fcvt.lu.s a5, ft5, rtz
36 fcvt.s.l ft6, a6, rdn
[all …]
H A Drv64zfh-valid.s10 # CHECK-ASM-AND-OBJ: fcvt.l.h a0, ft0, dyn
13 fcvt.l.h a0, ft0, dyn
14 # CHECK-ASM-AND-OBJ: fcvt.lu.h a1, ft1, dyn
17 fcvt.lu.h a1, ft1, dyn
18 # CHECK-ASM-AND-OBJ: fcvt.h.l ft2, a2, dyn
21 fcvt.h.l ft2, a2, dyn
25 fcvt.h.lu ft3, a3, dyn
30 fcvt.l.h a4, ft4, rne
33 fcvt.lu.h a5, ft5, rtz
36 fcvt.h.l ft6, a6, rdn
[all …]
H A Drv64d-aliases-valid.s16 # CHECK-INST: fcvt.l.d a0, ft0, dyn
17 # CHECK-ALIAS: fcvt.l.d a0, ft0{{[[:space:]]}}
18 fcvt.l.d a0, ft0
19 # CHECK-INST: fcvt.lu.d a1, ft1, dyn
20 # CHECK-ALIAS: fcvt.lu.d a1, ft1{{[[:space:]]}}
21 fcvt.lu.d a1, ft1
22 # CHECK-INST: fcvt.d.l ft3, a3, dyn
23 # CHECK-ALIAS: fcvt.d.l ft3, a3{{[[:space:]]}}
24 fcvt.d.l ft3, a3
25 # CHECK-INST: fcvt.d.lu ft4, a4, dyn
[all …]
H A Drv64f-aliases-valid.s16 # CHECK-INST: fcvt.l.s a0, ft0, dyn
17 # CHECK-ALIAS: fcvt.l.s a0, ft0{{[[:space:]]}}
18 fcvt.l.s a0, ft0
19 # CHECK-INST: fcvt.lu.s a1, ft1, dyn
20 # CHECK-ALIAS: fcvt.lu.s a1, ft1{{[[:space:]]}}
21 fcvt.lu.s a1, ft1
22 # CHECK-INST: fcvt.s.l ft2, a2, dyn
23 # CHECK-ALIAS: fcvt.s.l ft2, a2{{[[:space:]]}}
24 fcvt.s.l ft2, a2
25 # CHECK-INST: fcvt.s.lu ft3, a3, dyn
[all …]
H A Drv64zfinx-valid.s10 # CHECK-ASM-AND-OBJ: fcvt.l.s a0, t0, dyn
13 fcvt.l.s a0, t0, dyn
14 # CHECK-ASM-AND-OBJ: fcvt.lu.s a1, t1, dyn
17 fcvt.lu.s a1, t1, dyn
18 # CHECK-ASM-AND-OBJ: fcvt.s.l t2, a2, dyn
21 fcvt.s.l t2, a2, dyn
25 fcvt.s.lu t3, a3, dyn
31 fcvt.l.s a4, t4, rne
35 fcvt.lu.s a5, t5, rtz
39 fcvt.s.l t6, a6, rdn
[all …]
H A Drv64zhinx-valid.s10 # CHECK-ASM-AND-OBJ: fcvt.l.h a0, t0, dyn
13 fcvt.l.h a0, t0, dyn
14 # CHECK-ASM-AND-OBJ: fcvt.lu.h a1, t1, dyn
17 fcvt.lu.h a1, t1, dyn
18 # CHECK-ASM-AND-OBJ: fcvt.h.l t2, a2, dyn
21 fcvt.h.l t2, a2, dyn
25 fcvt.h.lu t3, a3, dyn
31 fcvt.l.h a4, t4, rne
35 fcvt.lu.h a5, t5, rtz
39 fcvt.h.l t6, a6, rdn
[all …]
H A Drv64d-valid.s10 # CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, dyn
13 fcvt.l.d a0, ft0, dyn
14 # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, dyn
17 fcvt.lu.d a1, ft1, dyn
22 # CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, dyn
25 fcvt.d.l ft3, a3, dyn
29 fcvt.d.lu ft4, a4, dyn
39 fcvt.d.l ft3, a3, rne
43 fcvt.d.lu ft4, a4, rtz
47 fcvt.l.d a0, ft0, rdn
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dinline-asm-f-abi-names.ll23 ; RV32IF-NEXT: fcvt.w.s a0, ft0
31 ; RV64IF-NEXT: fcvt.w.s a0, ft0
43 ; RV32IF-NEXT: fcvt.w.s a0, ft0
51 ; RV64IF-NEXT: fcvt.w.s a0, ft0
63 ; RV32IF-NEXT: fcvt.w.s a0, ft1
71 ; RV64IF-NEXT: fcvt.w.s a0, ft1
83 ; RV32IF-NEXT: fcvt.w.s a0, ft1
91 ; RV64IF-NEXT: fcvt.w.s a0, ft1
103 ; RV32IF-NEXT: fcvt.w.s a0, ft2
111 ; RV64IF-NEXT: fcvt.w.s a0, ft2
[all …]
H A Dinline-asm-d-abi-names.ll23 ; RV32IFD-NEXT: fcvt.w.d a0, ft0
31 ; RV64IFD-NEXT: fcvt.w.d a0, ft0
43 ; RV32IFD-NEXT: fcvt.w.d a0, ft0
51 ; RV64IFD-NEXT: fcvt.w.d a0, ft0
63 ; RV32IFD-NEXT: fcvt.w.d a0, ft1
71 ; RV64IFD-NEXT: fcvt.w.d a0, ft1
83 ; RV32IFD-NEXT: fcvt.w.d a0, ft1
91 ; RV64IFD-NEXT: fcvt.w.d a0, ft1
103 ; RV32IFD-NEXT: fcvt.w.d a0, ft2
111 ; RV64IFD-NEXT: fcvt.w.d a0, ft2
[all …]
H A Dhalf-convert-strict.ll22 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
27 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
111 ; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
219 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
226 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
233 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
240 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
250 ; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
255 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
260 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
[all …]
H A Dhalf-round-conv.ll10 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
15 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
25 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
30 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
54 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
56 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
118 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
120 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
182 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
184 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
[all …]
H A Drv64d-double-convert.ll6 ; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is
13 ; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
22 ; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
31 ; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
42 ; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
69 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
78 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
87 ; RV64ID-NEXT: fcvt.d.wu fa0, a0
96 ; RV64ID-NEXT: fcvt.d.w fa0, a0
105 ; RV64ID-NEXT: fcvt.d.w fa0, a0
[all …]
H A Ddouble-round-conv.ll10 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rdn
15 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
25 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rdn
30 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
40 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rdn
62 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
72 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn
77 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rdn
87 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn
134 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rup
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Dfcvt.s12 fcvt z0.h, p0/m, z0.s label
18 fcvt z0.h, p0/m, z0.d label
24 fcvt z0.s, p0/m, z0.h label
30 fcvt z0.s, p0/m, z0.d label
36 fcvt z0.d, p0/m, z0.h label
42 fcvt z0.d, p0/m, z0.s label
58 fcvt z5.d, p0/m, z0.s label
70 fcvt z5.d, p0/m, z0.s label

1234567