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/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparc-vis.s3 ! CHECK: fzeros %f31 ! encoding: [0xbf,0xb0,0x0c,0x20]
4 fzeros %f31
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
21 0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
44 0x46 0xce 0xfe 0x3a # CHECK: c.seq.ps $fcc6, $f31, $f14
55 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
58 0x46 0xd3 0xff 0xd3 # CHECK: movn.ps $f31, $f31, $19
61 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-vector.ll66 call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
74 ; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31
84 ; MIR32-DAG: STFD killed $f31, -8, $r1 :: (store (s64) into %fixed-stack.0)
96 ; MIR32-DAG: $f31 = LFD -8, $r1 :: (load (s64) from %fixed-stack.0)
103 ; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31
113 ; MIR64-DAG: STFD killed $f31, -8, $x1 :: (store (s64) into %fixed-stack.0)
125 ; MIR64-DAG: $f31 = LFD -8, $x1 :: (load (s64) from %fixed-stack.0)
168 …0},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},…
H A Dvsx-spill.ll21 …19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
44 ; CHECK-P9-FISL: stfd f31, -8(r1)
54 …19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
85 …0},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},…
H A Daix-csr.ll100 call void asm sideeffect "", "~{r13},~{r14},~{r25},~{r31},~{f14},~{f19},~{f21},~{f31}"()
108 ; MIR64-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variabl…
133 ; MIR32-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variabl…
159 ; MIR64: liveins: $x3, $x14, $x25, $x31, $f14, $f19, $f21, $f31
170 ; MIR64-DAG: STFD killed $f31, 392, $x1 :: (store (s64) into %fixed-stack.0)
175 ; MIR64-DAG: $f31 = LFD 392, $x1 :: (load (s64) from %fixed-stack.0)
188 ; MIR32: liveins: $r3, $r13, $r14, $r25, $r31, $f14, $f19, $f21, $f31
200 ; MIR32-DAG: STFD killed $f31, 280, $r1 :: (store (s64) into %fixed-stack.0)
205 ; MIR32-DAG: $f31 = LFD 280, $r1 :: (load (s64) from %fixed-stack.0)
H A Daix-csr-vector-extabi.ll114 call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
131 ; MIR32-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variabl…
150 ; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31, $v20, $v26, $v31
157 ; MIR32-DAG: STFD killed $f31, 440, $r1 :: (store (s64) into %fixed-stack.3)
173 ; MIR32-DAG: $f31 = LFD 440, $r1 :: (load (s64) from %fixed-stack.3)
196 ; MIR64-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variabl…
215 ; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31, $v20, $v26, $v31
223 ; MIR64-DAG: STFD killed $f31, 536, $x1 :: (store (s64) into %fixed-stack.3)
238 ; MIR64-DAG: $f31 = LFD 536, $x1 :: (load (s64) from %fixed-stack.3)
H A Daix-csr-alloc.ll20 …der(F4RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27…
27 …der(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27…
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmips-reginfo-fp32.s33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-xfail-mips32.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
21 0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5-wrong-error.s21 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
30 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s21 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
30 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips5-wrong-error.s21 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
30 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips5-wrong-error.s24 … c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
33 … movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32r2.s10 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-float.ll28 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
72 ; O32-INV-NOT: sdc1 $f31,
91 ; N32-INV-NOT: sdc1 $f31,
104 ; N64-DAG: sdc1 [[F31:\$f31]], [[OFF31:[0-9]+]]($sp)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
60 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
90 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
118 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-xfail-mips32r3.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
21 0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
78 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-xfail-mips32r5.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
21 0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
78 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-xfail-mips32r2.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
17 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
21 0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
78 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s108 .word f31(GOT_PREL) + (. - .Lsym)
110 @CHECK: 80 R_ARM_GOT_PREL f31
/llvm-project-15.0.7/lldb/test/Shell/ObjectFile/Breakpad/Inputs/
H A Didentification-macosx.syms5 STACK CFI f31 $rbp: .cfa -16 + ^ .cfa: $rsp 16 +
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5-wrong-error.s21 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
30 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/MachO/
H A Ddisassemble-stripped.test5 CHECK: 0000000100000f31 movq %rsp, %rbp
/llvm-project-15.0.7/compiler-rt/lib/builtins/ppc/
H A DsaveFP.S37 stfd f31,-8(r1)
H A DrestFP.S39 lfd f31,-8(r1)

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