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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-vector.ll66 call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
74 ; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31
83 ; MIR32-DAG: STFD killed $f21, -88, $r1 :: (store (s64) into %fixed-stack.1)
95 ; MIR32-DAG: $f21 = LFD -88, $r1 :: (load (s64) from %fixed-stack.1)
103 ; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31
112 ; MIR64-DAG: STFD killed $f21, -88, $x1 :: (store (s64) into %fixed-stack.1)
124 ; MIR64-DAG: $f21 = LFD -88, $x1 :: (load (s64) from %fixed-stack.1)
168 …9},~{f10},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
H A Daix-csr.ll100 call void asm sideeffect "", "~{r13},~{r14},~{r25},~{r31},~{f14},~{f19},~{f21},~{f31}"()
111 ; MIR64-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variabl…
136 ; MIR32-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variabl…
159 ; MIR64: liveins: $x3, $x14, $x25, $x31, $f14, $f19, $f21, $f31
169 ; MIR64-DAG: STFD killed $f21, 312, $x1 :: (store (s64) into %fixed-stack.1)
176 ; MIR64-DAG: $f21 = LFD 312, $x1 :: (load (s64) from %fixed-stack.1)
188 ; MIR32: liveins: $r3, $r13, $r14, $r25, $r31, $f14, $f19, $f21, $f31
199 ; MIR32-DAG: STFD killed $f21, 200, $r1 :: (store (s64) into %fixed-stack.1)
206 ; MIR32-DAG: $f21 = LFD 200, $r1 :: (load (s64) from %fixed-stack.1)
H A Daix-csr-vector-extabi.ll114 call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
134 ; MIR32-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variabl…
150 ; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31, $v20, $v26, $v31
156 ; MIR32-DAG: STFD killed $f21, 360, $r1 :: (store (s64) into %fixed-stack.4)
172 ; MIR32-DAG: $f21 = LFD 360, $r1 :: (load (s64) from %fixed-stack.4)
199 ; MIR64-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variabl…
215 ; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31, $v20, $v26, $v31
222 ; MIR64-DAG: STFD killed $f21, 456, $x1 :: (store (s64) into %fixed-stack.4)
237 ; MIR64-DAG: $f21 = LFD 456, $x1 :: (load (s64) from %fixed-stack.4)
H A Daix-csr-alloc.ll20 …$f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17…
27 …$f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17…
H A Dvsx-spill.ll21 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
54 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
85 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dinlineasm-bad.ll5 ; CHECK: error: couldn't allocate input reg for constraint '{f21}'
10 …tail call void asm sideeffect "faddd $0,$1,$2", "{f21},{f0},{f0}"(double 9.0, double 10.0, double …
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-xfail-mips32.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
39 0x46 0xde 0xa8 0x3b # CHECK: c.ngl.ps $f21, $f30
42 0x46 0xc8 0xaf 0x36 # CHECK: c.ole.ps $fcc7, $f21, $f8
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
60 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
90 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
118 …~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
H A Dno-odd-spreg.ll32 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
56 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s71 .word f21(tlsldo)
73 @CHECK: 54 R_ARM_TLS_LDO32 f21
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5-wrong-error.s16 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s16 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips5-wrong-error.s16 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips5-wrong-error.s19 … c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
22 … c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/compiler-rt/lib/builtins/ppc/
H A DsaveFP.S27 stfd f21,-88(r1)
H A DrestFP.S29 lfd f21,-88(r1)
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dnumeric-reg-names-f.s112 # CHECK-NUMERIC: fsqrt.s f10, f21
113 # CHECK-NUMERIC-NEXT: fsqrt.s f10, f21
114 fsqrt.s fa0, f21
H A Dnumeric-reg-names-d.s112 # CHECK-NUMERIC: fsqrt.d f10, f21
113 # CHECK-NUMERIC-NEXT: fsqrt.d f10, f21
114 fsqrt.d fa0, f21
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-xfail-mips64r2.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-xfail-mips64r3.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-xfail-mips64r5.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-fpxx.ll13 …~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
38 ; O32-FPXX-INV-NOT: sdc1 $f21,
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_ppc_regs.h54 #define f21 21 macro
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_ppc_regs.h54 #define f21 21 macro

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