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Searched refs:enableSubRegLiveness (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZSubtarget.cpp96 bool SystemZSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness() function in SystemZSubtarget
H A DSystemZSubtarget.h136 bool enableSubRegLiveness() const override;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Subtarget.h131 bool enableSubRegLiveness() const override { in enableSubRegLiveness() function
H A DGCNSubtarget.h791 bool enableSubRegLiveness() const override { in enableSubRegLiveness() function
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp204 bool RISCVSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness() function in RISCVSubtarget
H A DRISCVSubtarget.h276 bool enableSubRegLiveness() const override;
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetSubtargetInfo.h299 virtual bool enableSubRegLiveness() const { return false; } in enableSubRegLiveness() function
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp241 bool PPCSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness() function in PPCSubtarget
H A DPPCSubtarget.h394 bool enableSubRegLiveness() const override;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.h270 bool enableSubRegLiveness() const override;
H A DHexagonSubtarget.cpp740 bool HexagonSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness() function in HexagonSubtarget
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSubtarget.h483 bool enableSubRegLiveness() const override;
H A DARMSubtarget.cpp388 bool ARMSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness() function in ARMSubtarget
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp44 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && in MachineRegisterInfo()