[SystemZ] Add support for tune-cpu attribute

clang (like gcc) has the `-mtune=` command line option. This option
adds the `"tune-cpu"` attribute to a function. The intended functionality
is that the

[SystemZ] Add support for tune-cpu attribute

clang (like gcc) has the `-mtune=` command line option. This option
adds the `"tune-cpu"` attribute to a function. The intended functionality
is that the scheduling model of that cpu is used. E.g. `-mtune=z15 -march=z14`
generates only instructions supported on z14 but uses the scheduling model
of z15 for it.
This PR adds the infrastructure to support this.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D128910

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[Target] Remove redundant member initialization (NFC)

Identified with readability-redundant-member-init.

Revert "[llvm] Remove redundant member initialization (NFC)"

This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

warning: base cl

Revert "[llvm] Remove redundant member initialization (NFC)"

This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

warning: base class ‘class llvm::MCParsedAsmOperand’ should be
explicitly initialized in the copy constructor [-Wextra]

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[llvm] Remove redundant member initialization (NFC)

Identified with readability-redundant-member-init.

[SystemZ] [NFC] Add SystemZELFFrameLowering and SystemZXPLINKFrameLowering classes.

This patch adds class SystemZFrameLowering which is a SystemZ-specific class
detailing special registers used by c

[SystemZ] [NFC] Add SystemZELFFrameLowering and SystemZXPLINKFrameLowering classes.

This patch adds class SystemZFrameLowering which is a SystemZ-specific class
detailing special registers used by calling conventions on the target.
SystemZELFFrameLowering and SystemZXPLINKFrameLowering implement this class
for ELF and XPLINK64 respectively. Previous functionality in SystemZFrameLowering
is moved to SystemZELFFrameLowering. SystemZXPLINKFrameLowering can then be
implemented in future patches.

Reviewed By: uweigand, Kai

Differential Revision: https://reviews.llvm.org/D108777

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[SystemZ] [NFC] Replace SpecialRegisters field with a unique_ptr instead of a raw pointer.

This patch replaces the SpecialRegisters field with a unique_ptr instead of a raw pointer. This is better p

[SystemZ] [NFC] Replace SpecialRegisters field with a unique_ptr instead of a raw pointer.

This patch replaces the SpecialRegisters field with a unique_ptr instead of a raw pointer. This is better practice, and allows us to remove the definition of the dtor for the SystemZSubtarget class.

Reviewed By: uweigand, Kai

Differential Revision: https://reviews.llvm.org/D108639

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[SystemZ] Add support for new cpu architecture - arch14

This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new pr

[SystemZ] Add support for new cpu architecture - arch14

This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch14 as host processor.
- Assembler/disassembler support for new instructions.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining __VEC__ == 10304.

Note: No currently available Z system supports the arch14
architecture. Once new systems become available, the
official system name will be added as supported -march name.

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[SystemZ] [z/OS] Add SystemZCallingConventionRegisters class

This patch adds the abstract class SystemZCallingConventionRegisters
which is a SystemZ-specific class detailing special registers used
b

[SystemZ] [z/OS] Add SystemZCallingConventionRegisters class

This patch adds the abstract class SystemZCallingConventionRegisters
which is a SystemZ-specific class detailing special registers used
by calling conventions on the target. SystemZELFRegisters and
SystemZXPLINK64Registers implement this class for ELF and XPLINK64
respectively.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D102370

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[X86][MC][Target] Initial backend support a tune CPU to support -mtune

This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute

[X86][MC][Target] Initial backend support a tune CPU to support -mtune

This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line.

This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned.

One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU.

I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning.

Differential Revision: https://reviews.llvm.org/D85165

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[SystemZ] Ensure -mno-vx disables any use of vector features

When passing the -vector feature to LLVM (or equivalently the
-mno-vx command line argument to clang), the intent is that
generated code

[SystemZ] Ensure -mno-vx disables any use of vector features

When passing the -vector feature to LLVM (or equivalently the
-mno-vx command line argument to clang), the intent is that
generated code must not use any vector features (in particular,
no vector registers must be used).

However, there are some cases where we still could generate
such uses; these are all related to some of the additional
vector features (like +vector-enhancements-1). Since none
of those features are actually usable with -vector, just make
sure we disable them all if -vector is given.

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Remove GlobalValue::getAlignment().

This function is deceptive at best: it doesn't return what you'd expect.
If you have an arbitrary GlobalValue and you want to determine the
alignment of that poin

Remove GlobalValue::getAlignment().

This function is deceptive at best: it doesn't return what you'd expect.
If you have an arbitrary GlobalValue and you want to determine the
alignment of that pointer, Value::getPointerAlignment() returns the
correct value. If you want the actual declared alignment of a function
or variable, GlobalObject::getAlignment() returns that.

This patch switches all the users of GlobalValue::getAlignment to an
appropriate alternative.

Differential Revision: https://reviews.llvm.org/D80368

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TargetLowering.h - remove unnecessary TargetMachine.h include. NFC

Replace with forward declaration and move dependency down to source files that actually need it.

Both TargetLowering.h and TargetM

TargetLowering.h - remove unnecessary TargetMachine.h include. NFC

Replace with forward declaration and move dependency down to source files that actually need it.

Both TargetLowering.h and TargetMachine.h are 2 of the most expensive headers (top 10) in the ClangBuildAnalyzer report when building llc.

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[SystemZ] Support -msoft-float

This is needed when building the Linux kernel.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D72189

Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly m

Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly mechanical from a custom clang-tidy check, with a lot of
manual fixups. It uncovers a lot of minor inefficiencies.

This doesn't actually modify StringRef yet, I'll do that in a follow-up.

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[SystemZ] Add support for new cpu architecture - arch13

This patch series adds support for the next-generation arch13
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the

[SystemZ] Add support for new cpu architecture - arch13

This patch series adds support for the next-generation arch13
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Assembler/disassembler support for new instructions.
- CodeGen for new instructions, including new LLVM intrinsics.
- Scheduler description for the new processor.
- Detection of arch13 as host processor.

Note: No currently available Z system supports the arch13
architecture. Once new systems become available, the
official system name will be added as supported -march name.

llvm-svn: 365932

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Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[SystemZ] New CL option to enable subreg liveness

This option is needed to enable subreg liveness tracking during register
allocation.

Review: Ulrich Weigand
https://reviews.llvm.org/D50779

llvm-s

[SystemZ] New CL option to enable subreg liveness

This option is needed to enable subreg liveness tracking during register
allocation.

Review: Ulrich Weigand
https://reviews.llvm.org/D50779

llvm-svn: 339776

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[SystemZ] Add support for IBM z14 processor (1/3)

This patch series adds support for the IBM z14 processor. This part includes:
- Basic support for the new processor and its features.
- Support for

[SystemZ] Add support for IBM z14 processor (1/3)

This patch series adds support for the IBM z14 processor. This part includes:
- Basic support for the new processor and its features.
- Support for new instructions (except vector 32-bit float and 128-bit float).
- CodeGen for new instructions, including new LLVM intrinsics.
- Scheduler description for the new processor.
- Detection of z14 as host processor.

Support for the new 32-bit vector float and 128-bit vector float
instructions is provided by separate patches.

llvm-svn: 308194

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[SystemZ] Add all remaining instructions

This adds all remaining instructions that were still missing, mostly
privileged and semi-privileged system-level instructions. These are
provided for use wi

[SystemZ] Add all remaining instructions

This adds all remaining instructions that were still missing, mostly
privileged and semi-privileged system-level instructions. These are
provided for use with the assembler and disassembler only.

This brings the LLVM assembler / disassembler to parity with the
GNU binutils tools.

llvm-svn: 306876

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[SystemZ] Add decimal floating-point instructions

This adds assembler / disassembler support for the decimal
floating-point instructions. Since LLVM does not yet have
support for decimal float type

[SystemZ] Add decimal floating-point instructions

This adds assembler / disassembler support for the decimal
floating-point instructions. Since LLVM does not yet have
support for decimal float types, these cannot be used for
codegen at this point.

llvm-svn: 304203

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[SystemZ] Add crypto instructions

This adds the set of message-security assist instructions for
assembler / disassembler use.

llvm-svn: 302645

[SystemZ] Support execution hint instructions

This adds assembler support for the instructions provided by the
execution-hint facility (NIAI and BP(R)P). This required adding
support for the new re

[SystemZ] Support execution hint instructions

This adds assembler support for the instructions provided by the
execution-hint facility (NIAI and BP(R)P). This required adding
support for the new relocation types for 12-bit and 24-bit PC-
relative offsets used by the BP(R)P instructions.

llvm-svn: 288031

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[SystemZ] Support load-and-trap instructions

This adds support for the instructions provided with the
load-and-trap facility.

llvm-svn: 288030

[SystemZ] Support load-and-zero-rightmost-byte facility

This adds support for the LZRF/LZRG/LLZRGF instructions that were
added on z13, and uses them for code generation were appropriate.

SystemZDA

[SystemZ] Support load-and-zero-rightmost-byte facility

This adds support for the LZRF/LZRG/LLZRGF instructions that were
added on z13, and uses them for code generation were appropriate.

SystemZDAGToDAGISel::tryRISBGZero is updated again to prefer LLZRGF
over RISBG where both would be possible.

llvm-svn: 286586

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[SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities

Summary: Add support for the z13 instructions LOCHI and LOCGHI which
conditionally load immediate values. Add target inst

[SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities

Summary: Add support for the z13 instructions LOCHI and LOCGHI which
conditionally load immediate values. Add target instruction info hooks so
that if conversion will allow predication of LHI/LGHI.

Author: RolandF

Reviewers: uweigand

Subscribers: zhanjunl

Commiting on behalf of Roland.

Differential Revision: http://reviews.llvm.org/D22117

llvm-svn: 275086

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