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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-mul.mir51 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
52 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
82 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
83 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
113 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
114 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
144 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
145 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
175 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
176 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
[all …]
H A Dselect-shufflevec-undef-mask-elt.mir26 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
30 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY]], %subreg.dsub
32 ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[COPY1]], %subreg.dsub
35 ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[LDRDui]], %subreg.dsub
37 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
H A Dselect-concat-vectors.mir24 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
26 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
57 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
59 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
83 ; CHECK: %concat:fpr128 = INSERT_SUBREG [[DEF]], %a, %subreg.dsub
106 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %b, %subreg.dsub
108 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %a, %subreg.dsub
H A Dselect-unmerge.mir24 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
27 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
29 …; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DUPi64_]], %subreg.dsub
154 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
156 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
158 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
174 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
268 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
323 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
349 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
[all …]
H A Dselect-insert-vector-elt.mir123 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
175 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
179 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
205 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
207 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
H A Dselect-extract-vector-elt-with-extend.mir41 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
92 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
167 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
193 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
266 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
291 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
H A Dselect-shuffle-vector.mir52 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
54 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
57 ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub
59 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
H A Dselect-build-vector.mir62 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
64 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
128 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
157 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
214 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
H A Dselect-frint-nofp16.mir49 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
51 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
53 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
81 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
H A Dselect-intrinsic-uaddlv.mir102 … ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UADDLVv4i32v]], %subreg.dsub
103 ; CHECK: %intrin:fpr64 = COPY [[INSERT_SUBREG]].dsub
H A Dselect-extract.mir17 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
H A Dcontract-store.mir94 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub
114 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub
H A Dselect-extract-vector-elt.mir24 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
110 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
266 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
H A Dselect-fmul-indexed.mir25 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub
H A Dsubreg-copy.mir49 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[LDRQui]].dsub
H A Dpostlegalizer-lowering-build-vector-to-dup.mir51 ; SELECT: %build_vector:fpr64 = COPY [[INSvi32gpr]].dsub
80 ; SELECT: %build_vector:fpr64 = COPY [[MOVIv2d_ns]].dsub
H A Dselect-trunc.mir97 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmips64-alu-instructions.s84 # CHECK: dsub $9, $6, $7 # encoding: [0x2e,0x48,0xc7,0x00]
109 dsub $9,$6,$7
124 # CHECK: dsub $9, $9, $3 # encoding: [0x2e,0x48,0x23,0x01]
135 dsub $9, $3
137 dsub $9, 10
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmachine-combiner-fmul-dup.mir140 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
158 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
205 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
223 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
402 %5:fpr128 = INSERT_SUBREG %6, %1, %subreg.dsub
510 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.dsub
517 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
535 %9:fpr128 = INSERT_SUBREG %10, %1, %subreg.dsub
542 %14:fpr64 = COPY %13.dsub
588 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
[all …]
H A Daarch64st1.mir90 %5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub
93 %8:fpr128 = INSERT_SUBREG %9, killed %7, %subreg.dsub
96 %11:fpr128 = INSERT_SUBREG %12, killed %10, %subreg.dsub
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp119 SubReg == AArch64::dsub); in isFPR64()
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
H A DAArch64InstrInfo.td5488 dsub))>;
5496 dsub))>;
5758 dsub)>;
5785 dsub)>;
5802 dsub)>;
5871 dsub)>;
6135 dsub))>;
6166 dsub))>;
6177 dsub))>;
6183 dsub))>;
[all …]
/llvm-project-15.0.7/llvm/test/MachineVerifier/
H A Dtest_insert_subreg.mir25 %4:fpr128 = INSERT_SUBREG %3:fpr128, %0:fpr32, %subreg.dsub
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm-float-helpers.c99 double dsub(double a, double b) { return a - b; } in dsub() function
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips64.s20 …dsub $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
21 …dsub $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…

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