| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | select-ld4.mir | 22 ; CHECK: $d2 = COPY %dst3
29 $d2 = COPY %dst3(<8 x s8>)
51 ; CHECK: $q2 = COPY %dst3
58 $q2 = COPY %dst3(<16 x s8>)
80 ; CHECK: $d2 = COPY %dst3
109 ; CHECK: $q2 = COPY %dst3
138 ; CHECK: $d2 = COPY %dst3
167 ; CHECK: $q2 = COPY %dst3
196 ; CHECK: $q2 = COPY %dst3
261 $d2 = COPY %dst3(s64)
[all …]
|
| /llvm-project-15.0.7/llvm/test/MC/M68k/Relocations/ |
| H A D | data-gotoff.s | 16 ; RELOC: R_68K_GOTPCREL16 dst3 0x0
17 ; INSTR: lea (dst3@GOTPCREL,%pc), %a5
18 ; FIXUP: fixup A - offset: 2, value: dst3@GOTPCREL, kind: FK_PCRel_2
19 lea (dst3@GOTPCREL,%pc), %a5
|
| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | ifcvt-iter-indbr.ll | 74 %dst3 = call i8* @bar(i32 3, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
80 indirectbr i8* %dst3, [label %bb1, label %bb2]
|
| /llvm-project-15.0.7/libc/test/src/__support/File/ |
| H A D | file_test.cpp | 265 MemoryView src3(initial_content, READ_SIZE), dst3(read_data, READ_SIZE); in TEST() local
266 EXPECT_MEM_EQ(src3, dst3); in TEST()
407 dst3(f->get_str() + sizeof(initial_content) + sizeof(data), sizeof(data)); in TEST() local
408 EXPECT_MEM_EQ(src3, dst3); in TEST()
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.td | 2081 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
2515 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2519 "\t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];", []>;
2521 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2525 "\t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];", []>;
2527 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2531 "\t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];", []>;
2533 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2537 "\t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];", []>;
2543 "\t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];", []>;
[all …]
|
| H A D | NVPTXIntrinsics.td | 2166 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2169 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2172 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2175 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2178 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2202 : VLDU_G_ELE_V4<"v4.u16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2205 : VLDU_G_ELE_V4<"v4.u32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2208 : VLDU_G_ELE_V4<"v4.b16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2211 : VLDU_G_ELE_V4<"v4.b32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2214 : VLDU_G_ELE_V4<"v4.f32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 902 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
904 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
942 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
962 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
964 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
1218 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1252 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1256 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1289 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1579 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/ |
| H A D | loadorder.ll | 921 %dst3 = getelementptr inbounds i16, i16* %dst0, i64 3
929 store i16 %mul48, i16* %dst3
1203 %dst3 = getelementptr inbounds i32, i32* %dst0, i64 3
1219 store i32 %m4, i32* %dst3
|