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/llvm-project-15.0.7/lld/test/ELF/Inputs/
H A Dmips-dynamic.s18 .globl data0
19 .type data0, @object
20 .size data0, 4
21 data0: label
/llvm-project-15.0.7/compiler-rt/test/tsan/
H A Dmemcmp_race.cpp5 char *data0 = new char[10]; variable
12 sink = memcmp(data0+5, data1, size); in Thread1()
20 memcpy(data0+5, data2, size); in Thread2()
26 print_address("addr=", 1, &data0[5]); in main()
/llvm-project-15.0.7/polly/test/ScheduleOptimizer/
H A Dvivid-vbi-gen-vivid_vbi_gen_sliced-before-llvmreduced.ll14 …%data0.014 = phi %struct.v4l2_sliced_vbi_data* [ null, %entry ], [ %incdec.ptr, %vivid_vbi_gen_tel…
15 …ptr inbounds %struct.v4l2_sliced_vbi_data, %struct.v4l2_sliced_vbi_data* %data0.014, i32 0, i32 0,…
16 …ptr inbounds %struct.v4l2_sliced_vbi_data, %struct.v4l2_sliced_vbi_data* %data0.014, i32 0, i32 0,…
23 …ptr inbounds %struct.v4l2_sliced_vbi_data, %struct.v4l2_sliced_vbi_data* %data0.014, i32 0, i32 0,…
30 …etelementptr inbounds %struct.v4l2_sliced_vbi_data, %struct.v4l2_sliced_vbi_data* %data0.014, i32 1
/llvm-project-15.0.7/lld/test/ELF/
H A Dmips-got-and-copy.s17 # CHECK-NEXT: 0x[[DATA0:[0-9A-F]+]] R_MIPS_COPY data0
36 # CHECK-NEXT: Name: data0
55 lui $t0,%hi(data0) # R_MIPS_HI16 - requires R_MISP_COPY relocation
56 addi $t0,$t0,%lo(data0)
57 lw $t0,%got(data0)($gp) # R_MIPS_GOT16 - requires GOT entry
H A Dmips-lo16-not-relative.s15 # CHECK-NEXT: 0x{{[0-9A-F]+}} R_MIPS_COPY data0
22 addi $t0, $t0, %lo(data0)
H A Dmips-plt-copy.s14 # CHECK-DAG: 0x{{[0-9A-F]+}} R_MIPS_COPY data0
63 lui $t0,%hi(data0) # R_MIPS_HI16 requires COPY rel for DSO defined data.
64 addi $t0,$t0,%lo(data0)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.fptrunc.round.ll6 define amdgpu_gs void @test_fptrunc_round_upward(float %a, i32 %data0, <4 x i32> %data1, half addrs…
18 define amdgpu_gs void @test_fptrunc_round_downward(float %a, i32 %data0, <4 x i32> %data1, half add…
30 define amdgpu_gs void @test_fptrunc_round_upward_multiple_calls(float %a, float %b, i32 %data0, <4 …
H A Dinvariant-image-load.ll19 …%data0 = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 1, i32 0, <8 x i32> %load, i32 0, i32 0…
20 …call void @llvm.amdgcn.image.store.1d.f32.i32(float %data0, i32 1, i32 0, <8 x i32> %store, i32 0,…
H A Dfail.llvm.fptrunc.round.ll4 define amdgpu_gs void @test_fptrunc_round_legalization(double %a, i32 %data0, <4 x i32> %data1, hal…
H A Dllvm.amdgcn.exp.ll629 %data0 = alloca <4 x float>, align 8, addrspace(5)
632 %data = select i1 %cmp, <4 x float> addrspace(5)* %data0, <4 x float> addrspace(5)* %data1
636 %ptr0 = getelementptr inbounds <4 x float>, <4 x float> addrspace(5)* %data0, i32 0, i32 0
/llvm-project-15.0.7/compiler-rt/lib/tsan/tests/rtl/
H A Dtsan_string.cpp19 char data0[7] = {1, 2, 3, 4, 5, 6, 7}; in TEST_F() local
21 MainThread().Memcpy(data+1, data0+1, 5); in TEST_F()
/llvm-project-15.0.7/llvm/test/tools/llvm-objcopy/ELF/
H A Dihex-writer-empty-sections.test16 ## .data0 address
18 ## .data0 offset, contents, checksum
50 - Name: .data0
55 ## An empty section that's placed at the end of .data0. This won't be in the
130 ## .data0 sections, with empty bookends.
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DDSInstructions.td82 bits<10> data0;
101 " $data0$offset$gds"> {
112 " $addr, $data0$offset$gds"> {
141 " $addr, $data0, $data1$offset$gds"> {
163 " $addr, $data0, $data1$offset0$offset1$gds"> {
183 (ins src_op:$data0, offset:$offset),
184 " $vdst, $data0$offset gds"> {
199 " $vdst, $addr, $data0$offset$gds"> {
235 " $vdst, $addr, $data0, $data1$offset$gds"> {
395 " $data0$offset gds"> {
[all …]
H A DSILoadStoreOptimizer.cpp1003 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
1191 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1193 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
H A DSIInsertWaitcnts.cpp551 AMDGPU::OpName::data0) != -1) { in updateByEvent()
554 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0), in updateByEvent()
H A DSIInstrInfo.cpp324 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0); in getMemOperandsWithOffsetWidth()
348 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0); in getMemOperandsWithOffsetWidth()
360 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0); in getMemOperandsWithOffsetWidth()
4600 uint16_t DataNameIdx = isDS(Opcode) ? AMDGPU::OpName::data0 in verifyInstruction()
4648 if (!isAlignedReg(AMDGPU::OpName::data0)) { in verifyInstruction()
4821 (TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in getRegClass()
5036 isDS(Opc) ? AMDGPU::OpName::data0 : AMDGPU::OpName::vdata); in isOperandLegal()
H A DAMDGPUInstructionSelector.cpp1482 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::data0); in selectDSGWSIntrinsic()
H A DSIISelLowering.cpp3546 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) in emitGWSMemViolTestLoop()
4342 TII->enforceOperandRCAlignment(MI, AMDGPU::OpName::data0); in EmitInstrWithCustomInserter()
/llvm-project-15.0.7/lldb/unittests/Utility/
H A DReproducerTest.cpp161 YamlData data0(0); in TEST() local
176 recorder->Record(data0); in TEST()
/llvm-project-15.0.7/flang/runtime/
H A Dedit-output.cpp21 const unsigned char *data0, std::size_t bytes) { in EditBOZOutput() argument
31 const unsigned char *data{data0 + (isHostLittleEndian ? bytes - 1 : 0)}; in EditBOZOutput()
H A Dio-stmt.cpp486 bool IoStatementState::EmitEncoded(const CHAR *data0, std::size_t chars) { in EmitEncoded() argument
489 const UnsignedChar *data{reinterpret_cast<const UnsignedChar *>(data0)}; in EmitEncoded()
505 return Emit(data0, chars); in EmitEncoded()
/llvm-project-15.0.7/llvm/test/Verifier/AMDGPU/
H A Dintrinsic-immarg.ll7 …; CHECK-NEXT: %data0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs…
8 …%data0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 %bool, i1…
57 …; CHECK-NEXT: %data0 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 %dmask, float %…
58 …%data0 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 %dmask, float %vaddr, <8 x i3…
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp325 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in decodeOperand_AVLdSt_Any()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4317 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in validateAGPRLdSt()
4422 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0); in validateGWS()