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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dneon-bitwise-encoding.s176 vand d4, d7, d3
177 vand.8 d4, d7, d3
178 vand.16 d4, d7, d3
179 vand.32 d4, d7, d3
180 vand.64 d4, d7, d3
182 vand.i8 d4, d7, d3
187 vand.s8 d4, d7, d3
202 vand.f d4, d7, d3
203 vand.d d4, d7, d3
234 vorr d4, d7, d3
[all …]
H A Dneon-vld-encoding.s13 vld1.32 {d5, d6, d7}, [r3]
14 vld1.64 {d6, d7, d8}, [r3:64]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
18 vld1.64 {d6, d7, d8, d9}, [r3:64]
40 vld1.32 {d5, d6, d7}, [r3]!
41 vld1.64 {d6, d7, d8}, [r3:64]!
45 vld1.32 {d5, d6, d7}, [r3], r6
124 vld2.8 {d4-d7}, [r0:64]!
131 vld2.8 {d4-d7}, [r0:64], r6
[all …]
H A Dneon-mul-accum-encoding.s41 vqdmlal.s16 q11, d11, d7[0]
42 vqdmlal.s16 q11, d11, d7[1]
43 vqdmlal.s16 q11, d11, d7[2]
44 vqdmlal.s16 q11, d11, d7[3]
48 @ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0x47,0x63,0xdb,0xf2]
49 @ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0x4f,0x63,0xdb,0xf2]
50 @ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0x67,0x63,0xdb,0xf2]
51 @ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0x6f,0x63,0xdb,0xf2]
H A Dneont2-mul-accum-encoding.s45 vqdmlal.s16 q11, d11, d7[0]
46 vqdmlal.s16 q11, d11, d7[1]
47 vqdmlal.s16 q11, d11, d7[2]
48 vqdmlal.s16 q11, d11, d7[3]
52 @ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0xdb,0xef,0x47,0x63]
53 @ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0xdb,0xef,0x4f,0x63]
54 @ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0xdb,0xef,0x67,0x63]
55 @ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0xdb,0xef,0x6f,0x63]
H A Dsingle-precision-fp.s8 vmul.f64 d6, d7, d8
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
22 vmls.f64 d8, d7, d6
27 vfnma.f64 d7, d8, d9
32 @ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
42 @ CHECK-ERRORS-NEXT: vfnma.f64 d7, d8, d9
79 vcvt.f64.u32 d7, s6
86 vcvt.s32.f64 d7, d8, #3
95 @ CHECK-ERRORS-NEXT: vcvt.f64.u32 d7, s6
109 @ CHECK-ERRORS-NEXT: vcvt.s32.f64 d7, d8, #3
H A Deh-directive-vsave.s50 .vsave {d0, d1, d2, d3, d4, d5, d6, d7}
51 vpush {d0, d1, d2, d3, d4, d5, d6, d7}
52 vpop {d0, d1, d2, d3, d4, d5, d6, d7}
63 .vsave {d2, d3, d4, d5, d6, d7}
64 vpush {d2, d3, d4, d5, d6, d7}
65 vpop {d2, d3, d4, d5, d6, d7}
H A Dneon-mul-encoding.s107 vmul.s16 d1, d7[3]
115 vmul.s16 q1, d7[3]
123 vmul.s16 d8, d1, d7[3]
124 vmul.u16 d7, d2, d1[1]
131 vmul.s16 q8, q1, d7[3]
139 @ CHECK: vmul.i16 d1, d1, d7[3] @ encoding: [0x6f,0x18,0x91,0xf2]
147 @ CHECK: vmul.i16 q1, q1, d7[3] @ encoding: [0x6f,0x28,0x92,0xf3]
155 @ CHECK: vmul.i16 d8, d1, d7[3] @ encoding: [0x6f,0x88,0x91,0xf2]
156 @ CHECK: vmul.i16 d7, d2, d1[1] @ encoding: [0x49,0x78,0x92,0xf2]
163 @ CHECK: vmul.i16 q8, q1, d7[3] @ encoding: [0x6f,0x08,0xd2,0xf3]
H A Dneon-vst-encoding.s62 vst3.16 {d6, d7, d8}, [r2]
75 vst3.p8 {d6, d7, d8}, [r8]!
80 vst3.32 {d5, d7, d9}, [r4]!
83 @ CHECK: vst3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x02,0xf4]
94 @ CHECK: vst3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x08,0xf4]
99 @ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4]
155 vst2.i16 {d7[1], d9[1]}, [r1]!
158 vst2.u32 {d5[0], d7[0]}, [r4:64], r7
179 vst3.16 {d6[1], d7[1], d8[1]}, [r2]
190 vst3.p8 {d6[1], d7[1], d8[1]}, [r8]!
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfloat_arithmetic_operations.mir139 liveins: $d6, $d7
142 ; FP32: liveins: $d6, $d7
149 ; FP64: liveins: $d6, $d7
156 %1:_(s64) = COPY $d7
168 liveins: $d6, $d7
171 ; FP32: liveins: $d6, $d7
185 %1:_(s64) = COPY $d7
197 liveins: $d6, $d7
214 %1:_(s64) = COPY $d7
226 liveins: $d6, $d7
[all …]
H A Dfcmp.mir46 liveins: $d6, $d7
49 ; FP32: liveins: $d6, $d7
51 ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
56 ; FP64: liveins: $d6, $d7
58 ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
63 %1:_(s64) = COPY $d7
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfloat_arithmetic_operations.mir148 liveins: $d6, $d7
151 ; FP32: liveins: $d6, $d7
158 ; FP64: liveins: $d6, $d7
165 %1:fprb(s64) = COPY $d7
179 liveins: $d6, $d7
182 ; FP32: liveins: $d6, $d7
196 %1:fprb(s64) = COPY $d7
210 liveins: $d6, $d7
227 %1:fprb(s64) = COPY $d7
241 liveins: $d6, $d7
[all …]
H A Dfcmp.mir605 liveins: $d6, $d7
631 liveins: $d6, $d7
657 liveins: $d6, $d7
693 liveins: $d6, $d7
729 liveins: $d6, $d7
765 liveins: $d6, $d7
801 liveins: $d6, $d7
837 liveins: $d6, $d7
873 liveins: $d6, $d7
909 liveins: $d6, $d7
[all …]
H A Dfloat_args.mir49 liveins: $d6, $d7
52 ; FP32: liveins: $d6, $d7
57 ; FP64: liveins: $d6, $d7
61 %1:fprb(s64) = COPY $d7
176 liveins: $d6, $d7
179 ; FP32: liveins: $d6, $d7
184 ; FP32: $d7 = COPY [[COPY1]]
191 ; FP64: liveins: $d6, $d7
196 ; FP64: $d7 = COPY [[COPY1]]
203 %1:fprb(s64) = COPY $d7
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir144 liveins: $d6, $d7
147 ; FP32: liveins: $d6, $d7
154 ; FP64: liveins: $d6, $d7
161 %1:_(s64) = COPY $d7
174 liveins: $d6, $d7
177 ; FP32: liveins: $d6, $d7
191 %1:_(s64) = COPY $d7
204 liveins: $d6, $d7
221 %1:_(s64) = COPY $d7
234 liveins: $d6, $d7
[all …]
H A Dfloat_args.mir48 liveins: $d6, $d7
51 ; FP32: liveins: $d6, $d7
56 ; FP64: liveins: $d6, $d7
60 %1:_(s64) = COPY $d7
171 liveins: $d6, $d7
174 ; FP32: liveins: $d6, $d7
179 ; FP32: $d7 = COPY [[COPY1]](s64)
186 ; FP64: liveins: $d6, $d7
191 ; FP64: $d7 = COPY [[COPY1]](s64)
198 %1:_(s64) = COPY $d7
[all …]
H A Dfcmp.mir50 liveins: $d6, $d7
53 ; FP32: liveins: $d6, $d7
55 ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
61 ; FP64: liveins: $d6, $d7
63 ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
69 %1:_(s64) = COPY $d7
/llvm-project-15.0.7/llvm/test/tools/llvm-profgen/Inputs/
H A Dcold-profile-trimming.raw.prof25 4007cf-4007d7:12
26 4007d7-4007d7:12
46 400792->4007d7:12
51 4007d7->4007bd:12
52 4007d7->4007cf:13
H A Dprofile-density.raw.prof25 4007cf-4007d7:12
26 4007d7-4007d7:12
H A Dprofile-density-cs.raw.prof147 7d7-7d7:2029
149 792->7d7:853
154 7d7->7cf:2097
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dpost-ra-kill-update.mir9 # CHECK: $d7 = S2_lsr_r_p_or killed $d7, killed $d1, $r9
26 $d7 = S2_asl_r_p $d0, $r13
29 $d7 = S2_lsr_r_p_or killed $d7, killed $d1, killed $r9
/llvm-project-15.0.7/llvm/test/MC/M68k/ShiftRotate/Classes/
H A DMxSR_DD.s21 ; CHECK: rol.b %d6, %d7
23 rol.b %d6, %d7
24 ; CHECK: rol.l %d7, %d1
26 rol.l %d7, %d1
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/longbranch/
H A Dbranch-limits-fp-micromips.mir48 - { reg: '$d7', virtual-reg: '' }
74 ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
93 ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
121 liveins: $d6, $d7
123 FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
148 - { reg: '$d7', virtual-reg: '' }
174 ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
188 ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
201 liveins: $d6, $d7
203 FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
H A Dbranch-limits-fp-mips.mir47 - { reg: '$d7', virtual-reg: '' }
73 ; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
94 ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
124 liveins: $d6, $d7
126 FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
151 - { reg: '$d7', virtual-reg: '' }
177 ; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
198 ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
228 liveins: $d6, $d7
230 FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfp128-calling-conv.ll10 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
18 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
27 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
33 ret fp128 %d7
36 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
45 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dv6-jumptable-clobber.mir34 i32 7, label %d7
68 d7: ; preds = %0
112 i32 7, label %d7
146 d7: ; preds = %0
223 '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
243 …), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.…
263 bb.8.d7:
321 '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
340 …), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.…
360 bb.8.d7:

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