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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsoft-sitofp.ll10 ret double %conv
18 ret float %conv
26 ret double %conv
34 ret float %conv
74 ret i64 %conv
82 ret i32 %conv
90 ret i64 %conv
98 ret i32 %conv
106 ret i64 %conv
114 ret i32 %conv
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dround-conv.ll10 ret i32 %conv
20 ret i64 %conv
30 ret i32 %conv
40 ret i64 %conv
50 ret i32 %conv
60 ret i64 %conv
70 ret i32 %conv
80 ret i64 %conv
90 ret i32 %conv
100 ret i64 %conv
[all …]
H A Darm64-fast-isel-conversion-fallback.ll10 ret i32 %conv
20 ret i32 %conv
31 ret half %conv
42 ret half %conv
53 ret half %conv
63 ret half %conv
73 ret half %conv
84 ret half %conv
95 ret half %conv
106 ret half %conv
[all …]
H A Darm64-fast-isel-conversion.ll87 ret i32 %conv;
96 ret i64 %conv;
161 ret i32 %conv
171 ret i16 %conv
181 ret i8 %conv
208 ret i32 %conv
217 ret i32 %conv
226 ret i32 %conv
235 ret i32 %conv
390 ret i8 %conv
[all …]
H A Dcomplex-int-to-fp.ll19 ret <2 x double> %conv
28 ret <2 x double> %conv
39 ret <2 x double> %conv
49 ret <2 x double> %conv
60 ret <2 x double> %conv
70 ret <2 x double> %conv
79 ret <2 x float> %conv
87 ret <2 x float> %conv
97 ret <2 x float> %conv
106 ret <2 x float> %conv
[all …]
H A Dcmp-to-cmn.ll22 %conv = sext i32 %b to i64
34 %conv = sext i16 %b to i64
46 %conv = zext i8 %b to i64
58 %conv = sext i32 %a to i64
81 %conv = sext i16 %b to i32
93 %conv = zext i8 %b to i32
105 %conv = sext i16 %a to i64
117 %conv = sext i16 %a to i32
157 %conv = zext i8 %a to i64
169 %conv = zext i8 %a to i32
[all …]
H A Dint-to-fp-no-neon.ll24 ret double %conv
42 ret float %conv
54 ret half %conv
72 ret double %conv
90 ret float %conv
102 ret half %conv
138 ret float %conv
150 ret half %conv
192 ret half %conv
237 ret half %conv
[all …]
H A Daarch64-smov-gen.ll13 %conv = sext i8 %elt to i32
14 ret i32 %conv
25 ret i64 %conv
36 ret i32 %conv
47 ret i64 %conv
58 ret i64 %conv
73 ret i32 %conv
86 ret i64 %conv
99 ret i32 %conv
112 ret i64 %conv
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dmultiple_reduction.ll408 %mul = mul nuw nsw i32 %conv, %conv
412 %add.1 = add nuw nsw i32 %conv, %conv.1
413 %mul.1 = mul nuw nsw i32 %conv.1, %conv.1
419 %mul.2 = mul nuw nsw i32 %conv.2, %conv.2
425 %mul.3 = mul nuw nsw i32 %conv.3, %conv.3
431 %mul.4 = mul nuw nsw i32 %conv.4, %conv.4
437 %mul.5 = mul nuw nsw i32 %conv.5, %conv.5
443 %mul.6 = mul nuw nsw i32 %conv.6, %conv.6
449 %mul.7 = mul nuw nsw i32 %conv.7, %conv.7
922 %mul = mul nuw nsw i32 %conv, %conv
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Darm32-round-conv.ll10 ret i32 %conv
19 ret i32 %conv
28 ret i32 %conv
37 ret i32 %conv
46 ret i32 %conv
55 ret i32 %conv
64 ret i32 %conv
73 ret i32 %conv
82 ret i32 %conv
91 ret i32 %conv
[all …]
H A Dsmul.ll322 %mul.0 = mul i32 %conv.0, %conv.1
335 %mul.0 = mul i32 %conv.0, %conv.1
348 %mul.0 = mul i32 %conv.1, %conv.0
359 %conv.1 = ashr i32 %b, 16
360 %mul.0 = mul i32 %conv.0, %conv.1
371 %conv.1 = ashr i32 %b, 16
372 %mul.0 = mul i32 %conv.1, %conv.0
388 %mul.0 = mul i32 %conv.0, %conv.1
389 %mul.1 = mul i32 %conv.0, %conv.2
405 %mul.0 = mul i32 %conv.0, %conv.1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/Windows/
H A Dlibcalls.ll6 %conv = fptosi float %f to i64
7 ret i64 %conv
15 %conv = fptoui float %f to i64
16 ret i64 %conv
24 %conv = sitofp i64 %i64 to float
25 ret float %conv
34 ret float %conv
43 ret i64 %conv
52 ret i64 %conv
61 ret double %conv
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dsext_zext_load.ll12 ret i16 %a.conv
24 ret i32 %a.conv
36 ret i64 %a.conv
49 ret i16 %a.conv
61 ret i32 %a.conv
73 ret i64 %a.conv
85 ret i16 %a.conv
97 ret i32 %a.conv
109 ret i64 %a.conv
121 ret i16 %a.conv
[all …]
H A Dint_to_fp.ll11 ret float %conv
22 ret float %conv
33 ret float %conv
45 ret float %conv
56 ret float %conv
67 ret float %conv
80 ret float %conv
101 ret float %conv
112 ret double %conv
123 ret double %conv
[all …]
H A Dfp_to_int.ll12 ret i8 %conv
24 ret i16 %conv
35 ret i32 %conv
47 ret i64 %conv
59 ret i8 %conv
71 ret i16 %conv
83 ret i32 %conv
103 ret i64 %conv
115 ret i8 %conv
127 ret i16 %conv
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfast-isel-conversion-p5.ll9 %conv = sitofp i32 %a to double
21 %conv = sitofp i64 %a to double
33 %conv = sitofp i16 %a to double
46 %conv = sitofp i8 %a to double
61 %conv = fptosi float %a to i32
65 store i32 %conv, i32* %b.addr, align 4
73 %conv = fptosi float %a to i64
85 %conv = fptosi double %a to i32
97 %conv = fptosi double %a to i64
111 %conv = fptoui float %a to i32
[all …]
H A Dfast-isel-conversion.ll20 %conv = sitofp i64 %a to float
37 %conv = sitofp i32 %a to float
56 %conv = sitofp i16 %a to float
77 %conv = sitofp i8 %a to float
98 %conv = sitofp i32 %a to double
118 %conv = sitofp i64 %a to double
154 %conv = sitofp i8 %a to double
176 %conv = uitofp i64 %a to float
190 %conv = uitofp i32 %a to float
209 %conv = uitofp i16 %a to float
[all …]
H A Dfloat-logic-ops.ll11 %conv = bitcast float %a to i32
12 %and = and i32 %conv, 2147483647
23 %conv = bitcast double %a to i64
24 %and = and i64 %conv, 9223372036854775807
35 %conv = bitcast <4 x float> %a to <4 x i32>
87 %conv = bitcast float %a to i32
88 %and = xor i32 %conv, -2147483648
99 %conv = bitcast double %a to i64
134 %conv = bitcast float %a to i32
135 %and = or i32 %conv, -2147483648
[all …]
H A Dppcf128sf.ll93 %conv = zext i1 %cmp to i32
94 %conv1 = trunc i32 %conv to i8
106 %conv = zext i1 %cmp to i32
107 %conv1 = trunc i32 %conv to i8
119 %conv = zext i1 %cmp to i32
120 %conv1 = trunc i32 %conv to i8
132 %conv = zext i1 %cmp to i32
133 %conv1 = trunc i32 %conv to i8
145 %conv = zext i1 %cmp to i32
158 %conv = zext i1 %cmp to i32
[all …]
H A Dfp-int-conversions-direct-moves.ll21 ret i8 %conv
37 ret float %conv
54 ret i8 %conv
87 ret i8 %conv
120 ret i8 %conv
153 ret i16 %conv
186 ret i16 %conv
219 ret i16 %conv
252 ret i16 %conv
285 ret i32 %conv
[all …]
H A Dvsx_scalar_ld_st.ll18 %conv = fptosi double %0 to i32
19 store volatile i32 %conv, i32* %ii, align 4
31 %conv = fptosi float %0 to i32
44 %conv = sitofp i32 %0 to double
57 %conv = sitofp i32 %0 to float
70 %conv = fptoui double %0 to i32
83 %conv = fptoui float %0 to i32
96 %conv = uitofp i32 %0 to double
109 %conv = uitofp i32 %0 to float
122 %conv = fptrunc double %0 to float
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A DzextLoad_and_sextLoad.ll12 %conv = zext i8 %0 to i32
13 ret i32 %conv
25 ret i32 %conv
37 ret i16 %conv
49 ret i16 %conv
62 ret i64 %conv
74 ret i32 %conv
86 ret i32 %conv
98 ret i16 %conv
110 ret i16 %conv
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dicmp-and-shift.ll16 ret i32 %conv
42 ret i32 %conv
68 ret i32 %conv
94 ret i32 %conv
122 ret i32 %conv
135 ret i32 %conv
146 ret i32 %conv
160 ret i32 %conv
186 ret i32 %conv
212 ret i32 %conv
[all …]
H A Ddouble-float-shrink-1.ll20 %conv = fpext float %f to double
32 %conv = fpext float %f to double
43 %conv = fpext float %f to double
55 %conv = fpext float %f to double
67 %conv = fpext float %f to double
79 %conv = fpext float %f to double
90 %conv = fpext float %f to double
102 %conv = fpext float %f to double
114 %conv = fpext float %f to double
126 %conv = fpext float %f to double
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Dtrunc_select_cmp.ll14 %conv = sext i8 %a to i32
15 %cmp = icmp slt i32 %conv, 109
32 %conv = sext i8 %a to i32
51 %conv = zext i8 %a to i32
70 %conv = zext i8 %a to i32
89 %conv = zext i8 %a to i32
108 %conv = sext i8 %a to i32
127 %conv = zext i8 %a to i32
144 %conv = sext i8 %a to i32
160 %conv = zext i8 %a to i32
[all …]

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