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Searched refs:composeSubRegIndices (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp350 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
359 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
H A DRegisterCoalescer.cpp432 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in INITIALIZE_PASS_DEPENDENCY()
589 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
590 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
1338 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), in reMaterializeTrivialDef()
1799 unsigned SubUseIdx = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in updateRegDefsUses()
2570 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes()
3029 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in usesLanes()
H A DDetectDeadLanes.cpp172 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
H A DTailDuplicator.cpp437 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(), in duplicateInstruction()
H A DMachineOperand.cpp79 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h642 unsigned composeSubRegIndices(unsigned a, unsigned b) const { in composeSubRegIndices() function
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp245 unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx); in getSubOperand64()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1547 SubRegIdx = TRI->composeSubRegIndices(SubRegIdx, in decomposeSubvectorInsertExtractToSubRegs()