Home
last modified time | relevance | path

Searched refs:chains (Results 1 – 25 of 80) sorted by relevance

1234

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcopy-cpsr.ll6 ; escape. However, for long ADCS chains (and last ditch fallback) the dependency
12 ; + We want 2 long ADCS chains
15 ; + We want both chains to write CPSR post-split (so that the copy can't be
17 ; + We want the chains to be long enough that duplicating them is expensive.
H A D2011-08-29-SchedCycle.ll12 ; If the libcalls are not serialized (i.e. both have chains which are dag
28 ; The right solution is to fix LegalizeType too chains the libcalls together.
H A Dtest-sharedidx.ll11 ; can form three address chains in place of the shared induction
H A Ddomain-conv-vmovs.ll78 ; use-def chains would be messed up. Primarily a compile-test (we used to
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/bugprone/
H A Dbranch-clone.rst6 Checks for repeated branches in ``if/else if/else`` chains, consecutive
35 The check also detects repeated branches in longer ``if/else if/else`` chains
86 Unlike if statements, the check does not detect chains of conditional
/llvm-project-15.0.7/polly/lib/External/ppcg/
H A DChangeLog13 - optionally group chains of statements
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2011-12-26-extractelement-duplicate-load.ll7 ; the chains correctly.
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dcmp-chains.ll4 ; Ensure chains of comparisons produce chains of `ccmp`
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/Transforms/
H A DPasses.td31 let summary = "Rewrite sequential chains of spv.CompositeInsert operations into "
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpeephole-opt-regseq-removal.mir7 # %5 from %0. These values come from the respective chains:
/llvm-project-15.0.7/llvm/test/Other/
H A Dcgscc-iterate-function-mutation.ll235 ; functions, but again include long chains instead of single nodes and ensure
236 ; we traverse the chains in the correct order.
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dpr33204.ll3 ; Ensure that loads that bypass memory def-use chains get added as users of the new
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dsmlad8.ll3 ; Mul with operands that are not simple load and sext/zext chains: this is not
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Di1-to-double.ll23 ; Verify the cases won't crash because of missing chains
H A Dcommon-chain.ll11 ; chains:
114 ; It can not be commoned to chains because we need a chain for a single address.
115 ; It is not profitable to common chains if not all addresses are in chains.
226 ; We need at least 4 addresses to common 2 chains to reuse at least 1 offset.
310 …diff between address 2 and address 1 is 2*offset, and this offset is not reused among other chains,
311 ; so we can not common any chains.
412 ; and address 5(2*offset), so we can not common chains for these addresses.
540 ; chains:
642 ; chains:
/llvm-project-15.0.7/llvm/test/Transforms/DeadArgElim/
H A Dmultdeadretval.ll3 ; run instcombine to fold insert/extractvalue chains and we run dce to clean up
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/hicpp/
H A Dmultiway-paths-covered.rst12 ``if-else if`` chains that miss a final ``else`` branch might lead to unexpected
/llvm-project-15.0.7/clang/docs/
H A DDataFlowSanitizerDesign.rst141 An origin tracking trace is a list of chains. Each chain has a stack trace
154 chains.
162 Other instructions do not create new chains, but simply propagate origin trace
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dliveness_chains.ll7 ; Make sure we need a single iteration to determine the chains are dead/alive.
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dcrash_vectorizeTree.ll7 ; This test used to crash because we were following phi chains incorrectly.
/llvm-project-15.0.7/flang/test/Fir/
H A Dmemref-data-flow.fir3 // Test that all load-store chains are removed
/llvm-project-15.0.7/clang/test/Modules/
H A Dredecl-merge.m106 // sure we're maintaining the declaration chains even when normal name
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Divchain-stress-X86.ll12 ; can form three address chains in place of the shared induction
/llvm-project-15.0.7/llvm/docs/
H A DLexicon.rst252 also `def/use chains <ProgrammersManual.html#iterating-over-def-use-use-def-chains>`_.
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/X86/
H A Dsubchain-interleaved.ll6 ; Vectorized subsets of the load/store chains in the presence of

1234