| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 4717 auto Hi = MIRBuilder.buildSelect( in narrowScalarShift()
4744 auto Lo = MIRBuilder.buildSelect( in narrowScalarShift()
5424 auto Select = MIRBuilder.buildSelect(NarrowTy, in narrowScalarSelect()
5430 auto Select = MIRBuilder.buildSelect( in narrowScalarSelect()
5994 MIRBuilder.buildSelect(Dst, Src, True, False); in lowerUITOFP()
6026 MIRBuilder.buildSelect(Dst, Src, True, False); in lowerSITOFP()
6096 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); in lowerFPTOUI()
6256 V = MIRBuilder.buildSelect(S32, CmpEGt30, in lowerFPTRUNC_F64_TO_F16()
6329 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); in lowerMinMax()
7054 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); in lowerAddSubSatToAddoSubo()
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| H A D | MachineIRBuilder.cpp | 777 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res, in buildSelect() function in MachineIRBuilder
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| H A D | CombinerHelper.cpp | 3192 Builder.buildSelect(Dst, SelectCond, FoldTrue, FoldFalse, MI.getFlags()); in applyFoldBinOpIntoSelect()
4887 return MIB.buildSelect(Ty, IsOne, LHS, Q); in buildUDivUsingMul()
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| H A D | IRTranslator.cpp | 1445 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2010 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull); in legalizeAddrSpaceCast()
2070 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFrint()
2096 auto Add = B.buildSelect(S64, And, One, Zero); in legalizeFceil()
2177 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
3473 Q = B.buildSelect(S32, Cond, B.buildAdd(S32, Q, One), Q); in legalizeUnsignedDIV_REM32Impl()
3474 R = B.buildSelect(S32, Cond, B.buildSub(S32, R, Y), R); in legalizeUnsignedDIV_REM32Impl()
3592 auto C3 = B.buildSelect(S32, CmpEq, C2, C1); in legalizeUnsignedDIV_REM64Impl()
3611 auto C6 = B.buildSelect( in legalizeUnsignedDIV_REM64Impl()
3626 auto Sel1 = B.buildSelect( in legalizeUnsignedDIV_REM64Impl()
3633 auto Sel2 = B.buildSelect( in legalizeUnsignedDIV_REM64Impl()
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| H A D | AMDGPURegisterBankInfo.cpp | 137 B.buildSelect(DstReg, SrcReg, True, False); in applyBank()
1985 auto S = B.buildSelect(EltTy, Cmp, in foldExtractEltToCmpSelect()
2090 Register Select = B.buildSelect(EltTy, Cmp, Op0, Op1).getReg(0); in foldInsertEltToCmpSelect()
2261 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
2262 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
2600 B.buildSelect(DefRegs[0], SrcReg, True, False); in applyMappingImpl()
2603 auto Sel = B.buildSelect(SelType, SrcReg, True, False); in applyMappingImpl()
2607 B.buildSelect(DstReg, SrcReg, True, False); in applyMappingImpl()
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| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | LegalizerHelperTest.cpp | 3508 auto Select = B.buildSelect(V4S8, Cond, Val0, Val1); in TEST_F()
3531 auto VSelect = B.buildSelect(V4S8, VCond, Val0, Val1); in TEST_F()
4152 auto Select = B.buildSelect(v2s32, Cond, Val0, Val1); in TEST_F()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 1144 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
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