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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td12 bits <5> Vu32;
14 bits <5> Rt32;
20 bits <7> Ii;
22 bits <5> Rs32;
24 bits <2> Pd4;
32 bits <2> Pd4;
36 bits <11> Ii;
41 bits <5> n1;
48 bits <2> Ii;
51 bits <6> II;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
71 bits<3> rd;
72 bits<3> rs;
84 bits<3> rt;
85 bits<3> rs;
96 bits<3> rd;
97 bits<3> rt;
110 bits<3> rd;
[all …]
H A DMicroMips32r6InstrFormats.td47 bits<3> rs;
58 bits<5> rs;
68 bits<5> rt;
69 bits<5> rs;
81 bits<5> rt;
82 bits<5> rs;
104 bits<2> rt;
116 bits<5> rd;
117 bits<5> rt;
143 bits<5> rd;
[all …]
H A DMipsMSAInstrFormats.td33 bits<3> m;
46 bits<4> m;
82 class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
93 class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
104 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
115 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
126 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
139 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
152 class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
351 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
[all …]
H A DMipsInstrFormats.td188 class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
189 bits<5> rt;
190 bits<5> rd;
204 class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
216 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
217 bits<5> rd;
289 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
350 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
442 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
681 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
[all …]
H A DMicroMipsDSPInstrFormats.td25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
37 bits<5> rt;
38 bits<5> rs;
48 bits<5> rt;
49 bits<5> rs;
50 bits<2> ac;
61 bits<5> rd;
62 bits<5> rs;
[all …]
H A DMips32r6InstrFormats.td177 bits<5> rs;
178 bits<5> rt;
205 bits<5> rt;
220 bits<5> fs;
221 bits<5> fd;
234 bits<5> ft;
235 bits<5> fs;
236 bits<5> fd;
249 bits<5> ft;
261 bits<5> ct;
[all …]
H A DMipsDSPInstrFormats.td66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
80 bits<5> rd;
81 bits<5> rs;
94 bits<5> rs;
95 bits<5> rt;
107 bits<5> rs;
108 bits<5> rt;
109 bits<5> rd;
[all …]
H A DMips16InstrFormats.td121 bits<3> rx;
138 bits<3> rx;
139 bits<3> ry;
204 class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
211 bits<1> l;
258 bits<2> f;
279 bits<1> f;
385 bits<1> s;
412 bits<1> X;
538 bits<1> f;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td79 bits<11> src0;
81 bits<11> src1;
85 bits<1> last;
115 bits<11> dst;
118 bits<1> clamp;
137 bits<2> omod;
150 bits<11> src2;
167 bits<11> src2;
370 bits<2> COND;
408 bits<2> COND;
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DBitsInit.td6 bits<2> opc = { 0, 1 };
7 bits<2> opc2 = { 1, 0 };
8 bits<1> opc3 = { 1 };
19 // CHECK: bits<2> a;
33 bits<3> D3 = { 0, 0 }; // type mismatch. RHS doesn't have enough bits
34 bits<3> D4 = { 0b00 }; // type mismatch. RHS doesn't have enough bits
37 bits<1> D7 = { 3 }; // type mismatch. LHS doesn't have enough bits
38 bits<2> D8 = { 0 }; // type mismatch. RHS doesn't have enough bits
40 bits<8> E;
52 bits<16> H;
[all …]
H A Darithmetic.td7 // CHECK: bits<8> add = { 0, 0, 0, 1, 1, 0, 0, 0 };
18 class A<bits<8> a, bits<2> b> {
20 bits<8> add = !add(a, b);
21 bits<8> sub = !sub(a, b);
22 bits<8> and = !and(a, b);
23 bits<8> or = !or(a, b);
24 bits<8> xor = !xor(a, b);
25 bits<8> srl = !srl(a, b);
26 bits<8> sra = !sra(a, b);
27 bits<8> shl = !shl(a, b);
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td131 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
154 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
210 class SCForm<bits<6> opcode, bits<1> xo,
814 class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
859 class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
1191 class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
1455 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1464 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1471 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
1610 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
[all …]
/llvm-project-15.0.7/clang/test/Sema/
H A Dbittest-intrinsics.c12 sink = _bittest(bits, bitidx); in x86()
13 sink = _bittestandcomplement(bits, bitidx); in x86()
14 sink = _bittestandreset(bits, bitidx); in x86()
15 sink = _bittestandset(bits, bitidx); in x86()
37 sink = _bittest(bits, bitidx); in x64()
38 sink = _bittestandcomplement(bits, bitidx); in x64()
39 sink = _bittestandreset(bits, bitidx); in x64()
40 sink = _bittestandset(bits, bitidx); in x64()
63 sink = _bittest(bits, bitidx); in arm()
65 sink = _bittestandreset(bits, bitidx); in arm()
[all …]
/llvm-project-15.0.7/libc/test/utils/FPUtil/
H A Dx86_long_double_test.cpp23 FPBits bits(0.0l); in TEST() local
28 bits.mantissa = i; in TEST()
34 bits.implicitBit = 1; in TEST()
39 bits.mantissa = i; in TEST()
45 bits.exponent = 1; in TEST()
50 bits.mantissa = i; in TEST()
56 bits.exponent = 1; in TEST()
61 bits.mantissa = i; in TEST()
67 bits.exponent = 0; in TEST()
71 bits.mantissa = i; in TEST()
[all …]
/llvm-project-15.0.7/libc/src/__support/FPUtil/x86_64/
H A DLongDoubleBits.h53 UIntType bits;
58 bits |= mantVal;
72 bits |= expVal;
93 bits |= sign1;
107 bits = bits & ((UIntType(1) << 80) - 1);
161 bits.set_sign(1);
162 return bits;
169 return bits;
176 bits.set_sign(1);
177 return bits;
[all …]
/llvm-project-15.0.7/clang/test/Analysis/
H A Dfields.c62 struct Bits bits; in testBitfields() local
69 bits.c = 1; in testBitfields()
77 bits.x = true; in testBitfields()
79 bits.b = 2; in testBitfields()
81 if (foo() && bits.c) // no-warning in testBitfields()
84 bits.inner.e = 50; in testBitfields()
85 if (foo() && bits.inner.e) // no-warning in testBitfields()
93 bits.inner = getInner(); in testBitfields()
95 if (foo() && bits.inner.e) // no-warning in testBitfields()
102 bits.inner.f = 1; in testBitfields()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrFormats.td30 bits<8> op;
71 bits<7> sx;
74 bits<7> sy;
120 bits<4> cf;
122 bits<7> sy;
124 bits<7> sz;
147 bits<7> sx;
149 bits<7> sy;
213 bits<7> sy;
215 bits<7> sz;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td50 bits<5> rj;
51 bits<5> rd;
63 bits<5> rk;
64 bits<5> rj;
65 bits<5> rd;
79 bits<5> rk;
80 bits<5> rj;
81 bits<5> rd;
96 bits<5> rk;
97 bits<5> rj;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td70 bits<5> rz;
83 bits<5> rz;
312 class I_5_XZ_SYNC<bits<6> sop, bits<5> pcode, string opStr, bits<1> S, bits<1> I>
432 class I_5_XZ_U2<bits<6> sop, bits<5> lsb, bits<5> msb, dag outs, dag ins,
460 class I_5_XZ_US<bits<6> sop, bits<5> lsb, bits<5> msb, string op,
465 class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
501 class I_5_IMM5<bits<6> opcode, bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
517 class R_YXZ<bits<6> opcode, bits<6> sop, bits<5> pcode, dag outs, dag ins,
584 class R_YX<bits<6> sop, bits<5> pcode, string op>
602 class R_XZ<bits<6> sop, bits<5> pcode, string op>
[all …]
H A DCSKYInstrFormats16Instr.td30 bits<3> rz;
31 bits<3> rx;
32 bits<3> ry;
43 bits<4> rz;
44 bits<4> rx;
56 bits<4> rz;
57 bits<4> rx;
69 bits<4> rz;
70 bits<4> rx;
82 bits<4> rz;
[all …]
/llvm-project-15.0.7/libc/src/__support/FPUtil/
H A DNearestIntegerOperations.h26 FPBits<T> bits(x); in trunc()
51 bits.set_mantissa((bits.get_mantissa() >> trim_size) << trim_size); in trunc()
52 return T(bits); in trunc()
58 FPBits<T> bits(x); in ceil()
61 if (bits.is_inf_or_nan() || bits.is_zero()) in ceil()
80 bits.set_mantissa((bits.get_mantissa() >> trim_size) << trim_size); in ceil()
97 FPBits<T> bits(x); in floor()
112 if (bits.is_inf_or_nan() || bits.is_zero()) in round()
141 bits.set_mantissa((bits.get_mantissa() >> trim_size) << trim_size); in round()
164 if (bits.is_inf_or_nan() || bits.is_zero()) in round_using_current_rounding_mode()
[all …]
H A DFPBits.h52 UIntType bits; member
57 bits |= mantVal; in set_mantissa()
65 bits |= expVal; in set_unbiased_exponent()
115 FPBits() : bits(0) {} in FPBits()
158 FPBits<T> bits; in inf() local
160 return bits; in inf()
164 FPBits<T> bits = inf(); in neg_inf() local
165 bits.set_sign(1); in neg_inf()
166 return bits; in neg_inf()
171 bits.set_mantissa(v); in build_nan()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td39 bits<5> rs1;
40 bits<5> rs2;
54 bits<10> imm;
55 bits<5> rd;
56 bits<5> rs1;
71 bits<5> rs2;
72 bits<5> rs1;
83 bits<3> rd;
96 bits<3> rd;
97 bits<3> rs1;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td17 bits<2> op;
39 bits<3> op2;
51 bits<5> rd;
72 bits<2> cc;
112 bits<5> rd;
113 bits<6> op3;
114 bits<5> rs1;
156 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
169 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
183 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
[all …]

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