Lines Matching refs:bits
25 field bits<64> Inst;
30 bits<8> op;
38 bits<1> VE_Vector = 0;
39 bits<1> VE_VLInUse = 0;
40 bits<3> VE_VLIndex = 0;
41 bits<1> VE_VLWithMask = 0;
58 field bits<64> SoftFail = 0;
68 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
70 bits<1> cx = 0;
71 bits<7> sx;
72 bits<1> cy = 1;
73 bits<7> sz; // defines sz prior to sy to assign from sz
74 bits<7> sy;
75 bits<1> cz = 1;
76 bits<32> imm32;
94 class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
100 class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
103 bits<2> ry = 0;
115 class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
117 bits<1> cx = 0;
118 bits<1> cx2 = 0;
119 bits<2> bpf = 0;
120 bits<4> cf;
121 bits<1> cy = 1;
122 bits<7> sy;
123 bits<1> cz = 1;
124 bits<7> sz;
125 bits<32> imm32;
144 class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
146 bits<1> cx = 0;
147 bits<7> sx;
148 bits<1> cy = 1;
149 bits<7> sy;
150 bits<1> cz = 1;
151 bits<7> sz; // m field places at the top sz field
152 bits<8> vx = 0;
153 bits<8> vz = 0;
154 bits<1> cw = 0;
155 bits<1> cw2 = 0;
156 bits<4> cfw = 0;
174 class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr,
177 bits<1> avo = 0;
178 bits<1> lf = 0;
179 bits<1> sf = 0;
180 bits<1> c2 = 0;
181 bits<1> c1 = 0;
182 bits<1> c0 = 0;
205 class RVM<bits<8>opVal, dag outs, dag ins, string asmstr,
208 bits<1> cx = 0;
209 bits<1> vc = 0;
210 bits<1> cs = 0;
211 bits<4> m = 0;
212 bits<1> cy = 1;
213 bits<7> sy;
214 bits<1> cz = 1;
215 bits<7> sz;
216 bits<8> vx;
217 bits<8> vy = 0;
218 bits<7> sw = 0;
244 class RV<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
246 bits<1> cx = 0;
247 bits<1> cx2 = 0;
248 bits<1> cs = 0;
249 bits<1> cs2 = 0;
250 bits<4> m = 0;
251 bits<1> cy = 1;
252 bits<7> sy;
253 bits<1> cz = 0;
254 bits<7> sz = 0;
255 bits<8> vx = 0;
256 bits<8> vy = 0;
257 bits<8> vz = 0;
258 bits<8> vw = 0;