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/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/AMDGPU/
H A Dkd-vgpr.s7 …N: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1-re-assemble
8 ; RUN: diff %t1 %t1-re-assemble
12 …N: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2-re-assemble
13 ; RUN: diff %t2 %t2-re-assemble
17 …N: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t3-re-assemble
18 ; RUN: diff %t3 %t3-re-assemble
H A Dkd-sgpr.s7 …N: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1-re-assemble
8 ; RUN: diff %t1 %t1-re-assemble
12 …N: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2-re-assemble
13 ; RUN: diff %t2 %t2-re-assemble
17 …N: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t3-re-assemble
18 ; RUN: diff %t3 %t3-re-assemble
/llvm-project-15.0.7/llvm/test/tools/llvm-objcopy/MachO/
H A Dreal-world-input-copy.test1 # RUN: llvm-mc -assemble -triple i386-apple-darwin9 -filetype=obj %p/Inputs/macho.32.s -o %t.32.o
5 # RUN: llvm-mc -assemble -triple x86_64-apple-darwin9 -filetype=obj %p/Inputs/macho.64.s -o %t.64.o
11 # RUN: llvm-mc -assemble -triple x86_64-apple-darwin9 -filetype=obj %p/Inputs/various-symbols.s -o …
H A Dindirect-symbol-table-copy.s4 # RUN: llvm-mc -assemble -triple x86_64-apple-darwin9 -filetype=obj %s -o %t
/llvm-project-15.0.7/llvm/tools/llvm-mc-assemble-fuzzer/
H A DCMakeLists.txt10 add_llvm_fuzzer(llvm-mc-assemble-fuzzer
11 llvm-mc-assemble-fuzzer.cpp
/llvm-project-15.0.7/llvm/test/MC/COFF/
H A Dassoc-private.s3 # PR38607: We assemble this, and make .CRT$XCU comdat with .rdata even though
4 # .rdata isn't comdat. It's not clear what the semantics are, but we assemble
/llvm-project-15.0.7/llvm/test/MC/Disassembler/RISCV/
H A Dbranch-targets.txt1 # RUN: llvm-mc -assemble -triple riscv32 -mattr=+c -filetype=obj %s -o - 2>&1 | \
3 # RUN: llvm-mc -assemble -triple riscv64 -mattr=+c -filetype=obj %s -o - 2>&1 | \
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dattribute-with-option.s7 ## use rv32i to assemble the file instead of rv32e.
14 ## Use RV32I to assemble, since it will not trigger an assembly error.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc64-acc-regalloc-bugfix.ll14 …%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <…
21 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dudf.s1 # RUN: llvm-mc -assemble -show-encoding -triple=aarch64- %s | FileCheck %s
H A Dudf_not.s1 # RUN: not llvm-mc -assemble -show-encoding -triple=aarch64- %s 2>&1 | FileCheck %s
H A DCheckDataSymbol.s1 # RUN: llvm-mc -filetype=obj -assemble \
/llvm-project-15.0.7/llvm/test/Assembler/
H A Dsource-filename.ll2 ; Make sure that llvm-as/llvm-dis properly assemble/disassemble the
H A Dsummary-flags2.ll1 ; Check that we can assemble/disassemble empty index with non-trivial flags
H A Dsource-filename-backslash.ll1 ; Make sure that llvm-as/llvm-dis properly assemble/disassemble the
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddirective-fpu-softvfp.s5 @ Expected result: The integrated-as should be able to assemble this file
H A Dthumb2-exception-return-mclass.s1 # RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s
H A DCheckDataSymbol.s1 # RUN: llvm-mc -filetype=obj -assemble \
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dudf.txt3 # RUN: llvm-mc -assemble -filetype=obj -arch aarch64 -o - | \
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfunction-subtarget-features-2.ll3 ; This test verifies that we assemble code for different architectures
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dmusttail-valid.ll3 ; Should assemble without error.
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Daarch64-addp-upgrade.ll3 ; Bitcode was generated from file below, which may or may not even assemble any
H A Dintrinsics-with-unnamed-types.ll3 ; Make sure we can assemble and disassemble IR containing intrinsics with
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dmemory-addr64.ll3 ; Test that basic memory operations assemble as expected with 64-bit addresses.
H A Dmemory-addr32.ll3 ; Test that basic memory operations assemble as expected with 32-bit addresses.

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