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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-stack-objects.ll14 i64 %arg7, i64 %arg8, i64* byval(i64) %arg9) {
20 …K: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY8]](p0) :: (dereferenceable load (s64) from %ir.arg9)
22 ; CHECK: G_STORE [[ADD]](s64), [[COPY8]](p0) :: (volatile store (s64) into %ir.arg9)
24 %load = load i64, i64* %arg9
26 store volatile i64 %add, i64* %arg9
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dps-shader-arg-count.ll6 …g5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, floa…
16 …g5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, floa…
30 …g5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, floa…
44 …g5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, floa…
64 %i7 = extractelement <2 x float> %arg9, i32 1
110 %i7 = extractelement <2 x float> %arg9, i32 1
156 %i7 = extractelement <2 x float> %arg9, i32 1
197 …g5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, floa…
206 …g5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, floa…
288 %i7 = extractelement <2 x float> %arg9, i32 1
[all …]
H A Dret.ll45 …i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, floa…
70 …i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, floa…
84 …i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, floa…
103 …i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, floa…
132 …i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, floa…
161 …i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, floa…
H A Dcallee-special-input-vgprs-packed.ll332 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
348 store volatile i32 %arg9, i32 addrspace(1)* undef
434 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
439 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
459 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
475 store volatile i32 %arg9, i32 addrspace(1)* undef
587 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
607 store volatile i32 %arg9, i32 addrspace(1)* undef
685 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
705 store volatile i32 %arg9, i32 addrspace(1)* undef
H A Dcallee-special-input-vgprs.ll331 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
347 store volatile i32 %arg9, i32 addrspace(1)* undef
440 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
445 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
467 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
483 store volatile i32 %arg9, i32 addrspace(1)* undef
592 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
612 store volatile i32 %arg9, i32 addrspace(1)* undef
683 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
703 store volatile i32 %arg9, i32 addrspace(1)* undef
H A Dsmrd.ll138 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
154 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
177 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
198 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
218 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
234 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
250 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
270 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
290 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
306 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
[all …]
H A Dwait.ll17 …e(4)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(4)…
52 …)* inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
H A Dret_jump.ll24 …nreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, …
76 …nreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, …
H A Dsgpr-copy.ll8 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
32 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
172 …i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
225 …i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
289 …i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, …
327 …nreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, …
/llvm-project-15.0.7/flang/test/Semantics/
H A Dresolve82.f9029 subroutine testProcDecl(arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11) argument
41 procedure(procFunc), optional, pointer, optional :: arg9 local
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dfusion-2-level.mlir27 scf.for %arg9 = %c0 to %11 step %c3 {
30 …%16 = memref.subview %7[%arg10, %arg9][%c4, %c3][%c1, %c1]: memref<?x?xf32, offset: ?, strides: [?…
31 …%17 = memref.subview %8[%arg8, %arg9][%c2, %c3][%c1, %c1] : memref<?x?xf32, offset: ?, strides: [?…
H A Dsplit_reduction.mlir43 ^bb0(%arg7: f32, %arg8: f32, %arg9: f32):
46 %42 = arith.mulf %41, %arg9 : f32
H A Dfusion-elementwise-options.mlir45 ^bb0(%arg6 : f32, %arg7 : f32, %arg8 : f32, %arg9 : f32):
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/SystemZ/
H A Dvararg-kernel.ll21 %arg9 = call i32 () @random_i32()
28 i64 7, double 8.0, i32 zeroext %arg9,
45 ; - overflow@184 == i32 zext %arg9 - shadow is zero-extended
H A Dvararg.ll48 %arg9 = call i32 () @random_i32()
55 i64 7, double 8.0, i32 zeroext %arg9,
73 ; - overflow@160 == i32 zext %arg9 - shadow is zero-extended
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dstatepoint-ra.ll29 …le %arg4, double %arg5, double %arg6, double %arg7, double %arg8, double %arg9, double %arg10, dou…
31 …g7, i32 7, ptr null, i32 4, double %arg8, i32 7, ptr null, i32 4, double %arg9, i32 7, ptr null, i…
35 …arg9, double %arg10, double %arg11, i32 0, i32 0) [ "deopt"(i32 0, i32 2, i32 0, i32 70, i32 0, i3…
45 …6, i32 7, ptr null, i32 4, double %tmp17, i32 7, ptr null, i32 4, double %arg9, i32 7, ptr null, i…
49 …arg9, double %arg10, double %tmp18, i32 51, i32 0, i32 0) [ "deopt"(i32 0, i32 2, i32 0, i32 97, i…
H A Dfma-commute-loop.ll4 …2, ptr %arg3, ptr %arg4, ptr %arg5, i64 %arg6, i64 %arg7, i64 %arg8, i64 %arg9, i64 %arg10, i64 %a…
89 %tmp41 = add i64 %tmp21, %arg9
/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Daix-struct-arg.c85 void arg9(OverAligned x) {} in arg9() function
/llvm-project-15.0.7/mlir/test/Conversion/GPUToVulkan/
H A Dinvoke-vulkan.mlir49 …4, %arg2: i64, %arg6: !llvm.ptr<f32>, %arg7: !llvm.ptr<f32>, %arg8: i64, %arg9: i64, %arg10: i64) {
54 …%4 = llvm.insertvalue %arg9, %3[3, 0] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, arr…
/llvm-project-15.0.7/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
H A Dstratified-attrs-indexing.ll13 i32* %arg6, i32* %arg7, i32* %arg8, i32* %arg9, i32* %arg10,
/llvm-project-15.0.7/mlir/test/Dialect/Tensor/
H A Done-shot-bufferize.mlir186 %9 = scf.for %arg9 = %c0 to %c6 step %c1 iter_args(%arg10 = %2) -> (tensor<1x6x8xf32>) {
187 …%11 = tensor.extract_slice %8[0, %arg9, 0] [1, 1, 8] [1, 1, 1] : tensor<1x6x8xf32> to tensor<1x1x8…
188 …%12 = tensor.insert_slice %11 into %arg10[0, %arg9, 0] [1, 1, 8] [1, 1, 1] : tensor<1x1x8xf32> int…
/llvm-project-15.0.7/mlir/test/Dialect/LLVMIR/
H A Drocdl.mlir42 %arg8 : vector<16xi32>, %arg9 : vector<4xi32>,
108 %r12 = rocdl.mfma.i32.4x4x4i8 %arg3, %arg3, %arg9, %arg3, %arg3, %arg3 :
118 %r14 = rocdl.mfma.i32.16x16x16i8 %arg3, %arg3, %arg9, %arg3, %arg3, %arg3 :
184 %r27 = rocdl.mfma.i32.16x16x32.i8 %arg14, %arg14, %arg9, %arg3, %arg3, %arg3 :
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dloop-unswitch.mlir191 affine.for %arg9 = #flb0(%arg6) to #fub0(%arg6) {
197 affine.for %arg9 = #lb0(%arg6) to min #pub0(%arg6)[%sym] {
/llvm-project-15.0.7/mlir/test/Target/LLVMIR/
H A Drocdl.mlir57 %arg8 : vector<16 x i32>, %arg9 : vector<4xi32>,
123 %r12 = rocdl.mfma.i32.4x4x4i8 %arg3, %arg3, %arg9, %csti32, %csti32, %csti32 :
133 %r14 = rocdl.mfma.i32.16x16x16i8 %arg3, %arg3, %arg9, %csti32, %csti32, %csti32 :
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Damdgpu-abi-struct-coerce.cl501 …rg6, <2 x i16> noundef %arg7, <2 x i16> noundef %arg8, <2 x i16> noundef %arg9, <2 x i16> noundef …
504 short2 arg8, short2 arg9, short2 arg10, short2 arg11,
507 …rg6, <2 x i16> noundef %arg7, <2 x i16> noundef %arg8, <2 x i16> noundef %arg9, <2 x i16> noundef …
510 short2 arg8, short2 arg9, short2 arg10, short2 arg11,

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