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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.memcpy.ll21 ; LOOP-NEXT: buffer_load_ubyte v9, v[4:5], s[0:3], 0 addr64
23 ; LOOP-NEXT: buffer_load_ubyte v10, v[4:5], s[0:3], 0 addr64 offset:1
27 ; LOOP-NEXT: buffer_load_ubyte v10, v[4:5], s[0:3], 0 addr64 offset:2
28 ; LOOP-NEXT: buffer_load_ubyte v11, v[4:5], s[0:3], 0 addr64 offset:3
34 ; LOOP-NEXT: buffer_load_ubyte v10, v[4:5], s[0:3], 0 addr64 offset:4
35 ; LOOP-NEXT: buffer_load_ubyte v11, v[4:5], s[0:3], 0 addr64 offset:5
39 ; LOOP-NEXT: buffer_load_ubyte v11, v[4:5], s[0:3], 0 addr64 offset:6
40 ; LOOP-NEXT: buffer_load_ubyte v12, v[4:5], s[0:3], 0 addr64 offset:7
72 ; LOOP-NEXT: buffer_store_byte v9, v[6:7], s[0:3], 0 addr64
149 ; UNROLL-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64
[all …]
H A Dllvm.memcpy.inline.ll13 ; GCN-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64
15 ; GCN-NEXT: buffer_store_byte v4, v[0:1], s[0:3], 0 addr64
17 ; GCN-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64 offset:1
19 ; GCN-NEXT: buffer_store_byte v4, v[0:1], s[0:3], 0 addr64 offset:1
21 ; GCN-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64 offset:2
23 ; GCN-NEXT: buffer_store_byte v4, v[0:1], s[0:3], 0 addr64 offset:2
24 ; GCN-NEXT: buffer_load_ubyte v2, v[2:3], s[0:3], 0 addr64 offset:3
26 ; GCN-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:3
H A Dllvm.memmove.ll25 ; LOOP-NEXT: buffer_load_ubyte v8, v[6:7], s[0:3], 0 addr64
32 ; LOOP-NEXT: buffer_store_byte v8, v[6:7], s[0:3], 0 addr64
49 ; LOOP-NEXT: buffer_load_ubyte v8, v[6:7], s[0:3], 0 addr64
56 ; LOOP-NEXT: buffer_store_byte v8, v[6:7], s[0:3], 0 addr64
66 ; UNROLL-NEXT: buffer_load_ubyte v4, v[2:3], s[0:3], 0 addr64
67 ; UNROLL-NEXT: buffer_load_ubyte v5, v[2:3], s[0:3], 0 addr64 offset:1
68 ; UNROLL-NEXT: buffer_load_ubyte v6, v[2:3], s[0:3], 0 addr64 offset:2
69 ; UNROLL-NEXT: buffer_load_ubyte v2, v[2:3], s[0:3], 0 addr64 offset:3
71 ; UNROLL-NEXT: buffer_store_byte v4, v[0:1], s[0:3], 0 addr64
73 ; UNROLL-NEXT: buffer_store_byte v5, v[0:1], s[0:3], 0 addr64 offset:1
[all …]
H A Dmubuf-global.ll71 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
85 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
104 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
118 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
160 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
170 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
185 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
195 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
210 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
220 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
[all …]
H A Dllvm.memset.ll22 ; LOOP-NEXT: buffer_store_byte v2, v[5:6], s[0:3], 0 addr64
32 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64
33 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:1
34 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:2
35 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:3
H A Dload-constant.96.ll62 ; GFX7-UNALIGNED-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
72 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v2, v[0:1], s[4:7], 0 addr64 offset:1
81 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ubyte v11, v[0:1], s[4:7], 0 addr64
150 ; GFX7-UNALIGNED-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
163 ; GFX7-NOUNALIGNED-NEXT: buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64
197 ; GFX7-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
218 ; GFX7-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
239 ; GFX7-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
260 ; GFX7-NEXT: buffer_load_dwordx3 v[6:8], v[0:1], s[4:7], 0 addr64
300 ; GFX7-NEXT: buffer_load_dwordx3 v[0:2], v[0:1], s[4:7], 0 addr64
[all …]
/llvm-project-15.0.7/clang/test/Sema/
H A Darm-mve-immediates.c10 vldrdq_gather_base_s64(addr64, 0); in test_load_offsets()
11 vldrdq_gather_base_s64(addr64, 8); in test_load_offsets()
42 vstrdq_scatter_base(addr64, 0, addr64); in test_load_offsets()
43 vstrdq_scatter_base(addr64, 8, addr64); in test_load_offsets()
44 vstrdq_scatter_base(addr64, 2*8, addr64); in test_load_offsets()
45 vstrdq_scatter_base(addr64, 125*8, addr64); in test_load_offsets()
46 vstrdq_scatter_base(addr64, 126*8, addr64); in test_load_offsets()
47 vstrdq_scatter_base(addr64, 127*8, addr64); in test_load_offsets()
48 vstrdq_scatter_base(addr64, -125*8, addr64); in test_load_offsets()
49 vstrdq_scatter_base(addr64, -126*8, addr64); in test_load_offsets()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract-subvector-16bit.ll15 ; SI-NEXT: buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc
49 ; SI-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 glc
149 ; SI-NEXT: buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc
185 ; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc
286 ; SI-NEXT: buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc
323 ; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc
426 ; SI-NEXT: buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc
476 ; SI-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 glc
600 ; SI-NEXT: buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc
652 ; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc
[all …]
H A Dmad-combine.ll20 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
55 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
72 ; SI-STD-DAG: buffer_store_dword [[C]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$…
176 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
248 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
323 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
367 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
414 ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
456 ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
506 ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
[all …]
H A Dshader-addr64-nonuniform.ll6 ; addr64 mubuf with no readfirstlane.
12 ; SI: buffer_load_dwordx4 {{.*}} addr64
13 ; CI: buffer_load_dwordx3 {{.*}} addr64
26 ; SI: buffer_load_dwordx4 {{.*}} addr64
27 ; CI: buffer_load_dwordx3 {{.*}} addr64
41 ; SI: buffer_load_dwordx4 {{.*}} addr64
42 ; CI: buffer_load_dwordx3 {{.*}} addr64
56 ; SI: buffer_load_dwordx4 {{.*}} addr64
57 ; CI: buffer_load_dwordx3 {{.*}} addr64
71 ; SICI: buffer_load_dword {{.*}} addr64
[all …]
H A Dfma-combine.ll19 …dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
49 …AG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
50 …r_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
130 …AG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
131 …r_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
187 …AG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
188 …r_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
246 …AG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
247 …r_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
281 …AG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
[all …]
H A Dcommute_modifiers.ll8 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
22 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
37 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
52 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
67 ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
68 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
84 ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
85 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
101 ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
102 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
[all …]
H A Dshift-and-i128-ubfe.ll17 ; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64
24 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
48 ; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:4
55 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
81 ; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:8
88 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr64
112 ; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:12
119 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
142 ; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[8:9], s[4:7], 0 addr64
150 ; GCN-NEXT: buffer_store_dwordx4 v[4:7], v[8:9], s[0:3], 0 addr64
H A Dglobal_atomics_i64.ll78 …ic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
174 …ic_and_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
270 …ic_sub_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
366 …c_smax_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
462 …c_umax_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
558 …c_smin_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
655 …c_umin_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
751 …mic_or_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
966 …ic_xor_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
1121 …d_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[[[LO]]:[[HI]]], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
[all …]
H A Dglobal_atomics.ll40 ; SI: buffer_atomic_add v{{[0-9]+}}, v[[[PTRLO]]:[[PTRHI]]], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
119 ; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{…
218 ; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{…
318 ; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{…
418 ; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{…
517 ; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{…
615 ; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{…
712 ; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{…
810 ; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$…
918 ; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{…
[all …]
H A Dcombine-cond-add-sub.ll14 ; GCN-NEXT: buffer_load_dword v4, v[2:3], s[0:3], 0 addr64
18 ; GCN-NEXT: buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
56 ; GCN-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
97 ; GCN-NEXT: buffer_load_dword v4, v[2:3], s[0:3], 0 addr64
101 ; GCN-NEXT: buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
137 ; GCN-NEXT: buffer_load_dword v4, v[2:3], s[4:7], 0 addr64
142 ; GCN-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
181 ; GCN-NEXT: buffer_load_dword v4, v[2:3], s[4:7], 0 addr64
186 ; GCN-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
225 ; GCN-NEXT: buffer_load_dword v4, v[2:3], s[4:7], 0 addr64
[all …]
H A Dmadmk.ll12 …buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
13 …buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
31 …buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
32 …buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
33 …buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
63 …buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
64 …buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
130 …buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
131 …buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
152 …buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
[all …]
H A Dsalu-to-valu.ll22 ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
23 ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
93 ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 …
110 …buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
174 …ad_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
205 …ad_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
206 …ad_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32
207 …ad_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
208 …ad_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64
266 …r_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
[all …]
H A Dllvm.amdgcn.s.barrier.ll18 ; VARIANT0-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
24 ; VARIANT0-NEXT: buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
26 ; VARIANT0-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
39 ; VARIANT1-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
45 ; VARIANT1-NEXT: buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
47 ; VARIANT1-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
H A Dllvm.amdgcn.div.scale.ll9 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
10 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
29 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
30 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
49 …fer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
291 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
307 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
323 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
345 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
368 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
[all …]
H A Dshift-and-i64-ubfe.ll8 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
26 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 …
42 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
58 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
92 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 …
108 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
124 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
140 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
176 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 …
244 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dmubuf.s165 buffer_load_dword v1, v[2:3], s[4:7], s1 addr64
169 buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4
185 buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe
345 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64
365 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe
514 buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64
518 buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64
522 buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 slc
614 buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc
618 buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 glc
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dbuiltins-arm-exclusive.c8 int test_ldrex(char *addr, long long *addr64, float *addrfloat) { in test_ldrex() argument
44 sum += __builtin_arm_ldrex(addr64); in test_ldrex()
101 int test_ldaex(char *addr, long long *addr64, float *addrfloat) { in test_ldaex() argument
137 sum += __builtin_arm_ldaex(addr64); in test_ldaex()
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dpre-new-inst.ll14 %addr64 = bitcast %MyStruct* %addr to i64*
15 store i64 %in, i64* %addr64
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dpre-new-inst-xfail.ll15 %addr64 = bitcast %MyStruct* %addr to i64*
16 store i64 %in, i64* %addr64

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