| /llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 197 .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv)); in lowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 313 .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv)); in lowerCall()
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| H A D | X86ExpandPseudo.cpp | 241 .addRegMask(RegMask) in expandCALL_RVMARKER()
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| H A D | X86FastISel.cpp | 3501 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()
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| H A D | X86ISelLowering.cpp | 35179 .addRegMask(RegMask) in EmitLoweredSegAlloca()
35187 .addRegMask(RegMask) in EmitLoweredSegAlloca()
35196 .addRegMask(RegMask) in EmitLoweredSegAlloca()
35325 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
35337 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
35349 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
35662 MIB.addRegMask(RegInfo->getNoPreservedMask()); in emitEHSjLjSetJmp()
36109 .addRegMask(RI.getNoPreservedMask()); in EmitSjLjDispatchBlock()
36112 .addRegMask(RI.getNoPreservedMask()); in EmitSjLjDispatchBlock()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 980 MIB.addRegMask(Mask); in lowerTailCall()
1199 MIB.addRegMask(Mask); in lowerCall()
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| H A D | AArch64InstructionSelector.cpp | 3655 .addRegMask(TRI.getTLSCallPreservedMask()); in selectTLSGlobalValue()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 491 MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv)); in lowerCall()
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| H A D | ARMFastISel.cpp | 2281 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in ARMEmitLibcall()
2425 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in SelectCall()
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| H A D | ARMISelLowering.cpp | 10790 MIB.addRegMask(RI.getSjLjDispatchPreservedMask(*MF)); in EmitSjLjDispatchBlock()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 197 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const { in addRegMask() function
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 685 MIB.addRegMask(RegMask); in fuseCompareOperations()
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| H A D | SystemZInstrInfo.cpp | 757 .addRegMask(RegMask) in PredicateInstruction()
770 .addRegMask(RegMask) in PredicateInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 1188 MIB.addRegMask(Mask); in lowerTailCall()
1350 MIB.addRegMask(Mask); in lowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 491 MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv)); in lowerCall()
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| H A D | MipsFastISel.cpp | 1562 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 410 MIB.addRegMask(RM->getRegMask()); in AddOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2254 MIB.addRegMask(RegInfo->getNoPreservedMask()); in emitEHSjLjSetJmp()
2478 .addRegMask(RI.getNoPreservedMask()); in emitSjLjDispatchBlock()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1684 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()
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| H A D | PPCISelLowering.cpp | 11857 MIB.addRegMask(TRI->getNoPreservedMask()); in emitEHSjLjSetJmp()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3256 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); in fastLowerCall()
|