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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dloh.mir1 # RUN: llc -o /dev/null %s -mtriple=aarch64-apple-ios -run-pass=aarch64-collect-loh -debug-only=aar…
94 $x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
95 $x4 = LDRXui $x4, target-flags(aarch64-pageoff, aarch64-got) @g2
96 $x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
97 $x6 = LDRXui $x5, target-flags(aarch64-pageoff, aarch64-got) @g2
103 $x11 = ADRP target-flags(aarch64-page, aarch64-got) @g5
148 $x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
149 $x1 = LDRXui $x1, target-flags(aarch64-pageoff, aarch64-got) @g4
164 $x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
178 $x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
[all …]
H A Dsme-intrinsics-zero.ll265 call void @llvm.aarch64.sme.zero(i64 0)
266 call void @llvm.aarch64.sme.zero(i64 1)
267 call void @llvm.aarch64.sme.zero(i64 2)
268 call void @llvm.aarch64.sme.zero(i64 3)
269 call void @llvm.aarch64.sme.zero(i64 4)
270 call void @llvm.aarch64.sme.zero(i64 5)
271 call void @llvm.aarch64.sme.zero(i64 6)
272 call void @llvm.aarch64.sme.zero(i64 7)
273 call void @llvm.aarch64.sme.zero(i64 8)
274 call void @llvm.aarch64.sme.zero(i64 9)
[all …]
H A Dmisched-fusion-aes.ll1 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s
3 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s
23 declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %d)
25 declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %d)
37 %f00 = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %e00)
39 %f01 = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %e01)
41 %f02 = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %e02)
43 %f03 = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %e03)
47 %f10 = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %e00)
49 %f11 = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %e01)
[all …]
H A Dsve-coalesce-ptrue-intrinsics.ll2 ; RUN: opt -S -aarch64-sve-intrinsic-opts -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
4 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
5 declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg)
6 declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg)
7 declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
29 %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
31 %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
47 %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 0)
49 %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0)
70 %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 0)
[all …]
H A Dremat.ll1 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a34 -o - %s | FileCheck %s
2 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s | FileCheck %s
3 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
4 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s | FileCheck %s
5 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
6 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a65 -o - %s | FileCheck %s
8 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
9 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s | FileCheck %s
20 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=falkor -o - %s | FileCheck %s
22 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s | FileCheck %s
[all …]
H A Darm64-cvt.ll1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
58 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)
66 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)
74 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A)
90 %tmp3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %A)
[all …]
H A Darm64-neon-across.ll3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
23 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>)
35 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>)
[all …]
H A Dmachine-outliner-retaddr-sign-sp-mod.mir5 target triple = "aarch64-arm-linux-gnu"
75 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
76 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
77 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
78 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
79 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
80 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
110 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
111 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
112 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
[all …]
H A Dpreferred-function-alignment.ll1 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=generic < %s | FileCheck --check-prefixes=ALIGN2,CH…
2 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a35 < %s | FileCheck --check-prefixes=ALIGN4…
3 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a53 < %s | FileCheck --check-prefixes=ALIGN4…
4 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a55 < %s | FileCheck --check-prefixes=ALIGN4…
5 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 < %s | FileCheck --check-prefixes=ALIGN4…
6 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a65 < %s | FileCheck --check-prefixes=ALIGN3…
8 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a72 < %s | FileCheck --check-prefixes=ALIGN4…
12 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=a64fx < %s | FileCheck --check-prefixes=ALIGN3,CHEC…
13 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cyclone < %s | FileCheck --check-prefixes=ALIGN2,CH…
14 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=falkor < %s | FileCheck --check-prefixes=ALIGN2,CHE…
[all …]
H A Dsettag-merge.ll1 ; RUN: llc < %s -mtriple=aarch64 -mattr=+mte -aarch64-order-frame-objects=0 | FileCheck %s
4 declare void @llvm.aarch64.settag(i8* %p, i64 %a)
5 declare void @llvm.aarch64.settag.zero(i8* %p, i64 %a)
14 call void @llvm.aarch64.settag(i8* %a, i64 16)
15 call void @llvm.aarch64.settag(i8* %b, i64 16)
30 call void @llvm.aarch64.settag(i8* %a, i64 16)
31 call void @llvm.aarch64.settag(i8* %b, i64 16)
32 call void @llvm.aarch64.settag(i8* %c, i64 16)
33 call void @llvm.aarch64.settag(i8* %d, i64 16)
47 call void @llvm.aarch64.settag(i8* %a, i64 16)
[all …]
H A Darm64-fminv.ll6 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)
24 declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>)
25 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)
49 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
50 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
51 declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>)
74 declare float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float>)
75 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
99 declare float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float>)
[all …]
H A Darm64-vsqrt.ll1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
94 %tmp3 = call float @llvm.aarch64.neon.frecpe.f32(float %tmp1)
102 %tmp3 = call double @llvm.aarch64.neon.frecpe.f64(double %tmp1)
109 declare float @llvm.aarch64.neon.frecpe.f32(float) nounwind readnone
110 declare double @llvm.aarch64.neon.frecpe.f64(double) nounwind readnone
116 %tmp3 = call float @llvm.aarch64.neon.frecpx.f32(float %tmp1)
124 %tmp3 = call double @llvm.aarch64.neon.frecpx.f64(double %tmp1)
128 declare float @llvm.aarch64.neon.frecpx.f32(float) nounwind readnone
159 %tmp3 = call float @llvm.aarch64.neon.frsqrte.f32(float %tmp1)
167 %tmp3 = call double @llvm.aarch64.neon.frsqrte.f64(double %tmp1)
[all …]
H A Delim-dead-mi.mir1 # RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \
27 …%0:gpr64common = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) …
34 …%1:gpr64common = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) …
48 $x0 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c
58 …CHECK-NOT: %6:gpr64common = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, a…
59 …%6:gpr64common = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) …
H A Dv8.5a-scalar-frint3264-intrinsic.ll1 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.5a | FileCheck %s
3 declare float @llvm.aarch64.frint32z.f32(float)
4 declare double @llvm.aarch64.frint32z.f64(double)
5 declare float @llvm.aarch64.frint64z.f32(float)
6 declare double @llvm.aarch64.frint64z.f64(double)
13 %val = tail call float @llvm.aarch64.frint32z.f32(float %a)
31 %val = tail call float @llvm.aarch64.frint64z.f32(float %a)
44 declare float @llvm.aarch64.frint32x.f32(float)
45 declare double @llvm.aarch64.frint32x.f64(double)
46 declare float @llvm.aarch64.frint64x.f32(float)
[all …]
/llvm-project-15.0.7/llvm/lib/ExecutionEngine/JITLink/
H A DELF_aarch64.cpp74 using namespace aarch64; in getRelocationKind()
177 Kind = aarch64::Branch26; in addSingleRelocation()
181 Kind = aarch64::Page21; in addSingleRelocation()
251 Kind = aarch64::MoveWide16; in addSingleRelocation()
288 Kind = aarch64::Pointer64; in addSingleRelocation()
292 Kind = aarch64::Delta32; in addSingleRelocation()
296 Kind = aarch64::Delta64; in addSingleRelocation()
300 Kind = aarch64::GOTPage21; in addSingleRelocation()
515 aarch64::GOTTableManager GOT; in buildTables_ELF_aarch64()
557 ".eh_frame", 8, aarch64::Pointer32, aarch64::Pointer64, in link_ELF_aarch64()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AArch64/
H A Dtarget-flags.mir1 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
24 ; CHECK: $x8 = ADRP target-flags(aarch64-page) @var_i32
25 ; CHECK-NEXT: $x9 = ADRP target-flags(aarch64-page) @var_i64
26 ; CHECK-NEXT: $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
27 ; CHECK-NEXT: $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
29 ; CHECK: STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
30 $x8 = ADRP target-flags(aarch64-page) @var_i32
31 $x9 = ADRP target-flags(aarch64-page) @var_i64
32 $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
33 $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-blockaddress.mir2 # RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select…
8 target triple = "aarch64-none-linux-gnu"
33 …= MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-f…
34 …r:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, …
41 …; LARGE: [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@te…
42 …; LARGE: [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) bloc…
43 …; LARGE: [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blo…
45 ; LARGE: [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0
46 …; LARGE: [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @a…
47 …; LARGE: [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @a…
[all …]
H A Dselect-add-low.mir2 # RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck …
23 …ECK: %add_low:gpr64common = MOVaddr target-flags(aarch64-page) @x, target-flags(aarch64-pageoff, a…
27 %adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x
28 %add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
43 …K: %add_low:gpr64common = MOVaddr target-flags(aarch64-page) @x + 1, target-flags(aarch64-pageoff,…
47 %adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x + 1
48 %add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x + 1
64 ; CHECK: %add_low:gpr64sp = ADDXri %ptr, target-flags(aarch64-pageoff, aarch64-nc) @x, 0
68 %add_low:gpr(p0) = G_ADD_LOW %ptr(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/
H A Dsve-intrinsics-ptest.ll3 target triple = "aarch64-unknown-linux-gnu"
7 ; CHECK: %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 0)
11 %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 0)
21 ; CHECK: %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
25 %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
38 %mask = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 0)
61 %mask = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0)
68 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
69 declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
70 declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
[all …]
H A Dsve-intrinsic-opts-cmpne.ll3 target triple = "aarch64-unknown-linux-gnu"
10 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
15 %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
22 ; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
25 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
30 %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
375 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
376 declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
377 declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
378 declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
[all …]
H A Dsve-intrinsic-opts-counting-elems.ll4 target triple = "aarch64-unknown-linux-gnu"
14 %out = call i64 @llvm.aarch64.sve.cntb(i32 1)
22 %out = call i64 @llvm.aarch64.sve.cntb(i32 2)
30 %out = call i64 @llvm.aarch64.sve.cntb(i32 4)
38 %cnt = call i64 @llvm.aarch64.sve.cntb(i32 8)
47 %cnt = call i64 @llvm.aarch64.sve.cntb(i32 9)
58 %out = call i64 @llvm.aarch64.sve.cntb(i32 31)
70 %out = call i64 @llvm.aarch64.sve.cnth(i32 1)
78 %out = call i64 @llvm.aarch64.sve.cnth(i32 2)
86 %out = call i64 @llvm.aarch64.sve.cnth(i32 4)
[all …]
H A Dsve-intrinsic-loadstore.ll4 target triple = "aarch64-unknown-linux-gnu"
12 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
23 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
37 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 16)
51 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
64 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
75 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
89 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 16)
119 declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
120 declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
[all …]
H A Dsve-intrinsic-to-svbool-binops.ll4 target triple = "aarch64-unknown-linux-gnu"
13 …%t1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %a)
15 …%t3 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> …
25 …%t1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %a)
37 …%t1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %a)
127 declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)
128 declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
129 declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)
130 declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)
131 declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
[all …]
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dupgrade-aarch64-ldstxr.ll1 ; RUN: llvm-dis < %S/upgrade-aarch64-ldstxr.bc | FileCheck %s
4 ; CHECK: call i64 @llvm.aarch64.ldxr.p0i32(i32* elementtype(i32)
5 %a = call i64 @llvm.aarch64.ldxr.p0i32(i32* %p)
7 %c = call i32 @llvm.aarch64.stxr.p0i32(i64 0, i32* %p)
9 ; CHECK: call i64 @llvm.aarch64.ldaxr.p0i32(i32* elementtype(i32)
10 %a2 = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %p)
12 %c2 = call i32 @llvm.aarch64.stlxr.p0i32(i64 0, i32* %p)
16 declare i64 @llvm.aarch64.ldxr.p0i32(i32*)
17 declare i64 @llvm.aarch64.ldaxr.p0i32(i32*)
18 declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*)
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-isel-fuzzer/
H A Daarch64-execname-options.ll4 ; REQUIRES: aarch64-registered-target
12 ; RUN: rm -f %t.bin--aarch64
13 ; RUN: rm -f %t.bin--aarch64-O1
14 ; RUN: rm -f %t.bin--O3-aarch64
16 ; RUN: cp llvm-isel-fuzzer %t.bin--aarch64
17 ; RUN: %t.bin--aarch64 %t.input 2>&1 | FileCheck -check-prefix=AARCH64 %s
18 ; AARCH64: Injected args: -mtriple=aarch64
20 ; RUN: cp llvm-isel-fuzzer %t.bin--aarch64-O1
22 ; OPT-AFTER: Injected args: -mtriple=aarch64 -O1
24 ; RUN: cp llvm-isel-fuzzer %t.bin--O3-aarch64
[all …]

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