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/llvm-project-15.0.7/mlir/test/Dialect/MemRef/
H A Dfold-subview-ops.mlir12 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
13 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
14 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]+]]: index
15 // CHECK-SAME: %[[ARG4:[a-zA-Z0-9_]+]]: index
31 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
32 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
33 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]+]]: index
34 // CHECK-SAME: %[[ARG4:[a-zA-Z0-9_]+]]: index
35 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9_]+]]: index
36 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9_]+]]: index
[all …]
/llvm-project-15.0.7/polly/test/CodeGen/
H A Daliasing_parametric_simple_2.ll8 ; CHECK: %[[Ctx:[._a-zA-Z0-9]*]] = and i1 true
9 ; CHECK-NEXT: %[[M0:[._a-zA-Z0-9]*]] = sext i32 %c to i64
12 ; CHECK-NEXT: %[[OS0:[._a-zA-Z0-9]*]] = or i1 false, %[[M3O]]
14 ; CHECK-NEXT: %[[M1:[._a-zA-Z0-9]*]] = icmp sgt i64 6, %[[M3R]]
18 ; CHECK-NEXT: %[[BMaxI:[._a-zA-Z0-9]*]] = ptrtoint i32* %[[BMax]] to i64
22 ; CHECK-NEXT: %[[m0:[._a-zA-Z0-9]*]] = sext i32 %c to i64
25 ; CHECK-NEXT: %[[OS1:[._a-zA-Z0-9]*]] = or i1 %[[OS0]], %[[m3O]]
27 ; CHECK-NEXT: %[[m1:[._a-zA-Z0-9]*]] = icmp slt i64 5, %[[m3R]]
34 ; CHECK-NEXT: %[[RTC:[._a-zA-Z0-9]*]] = and i1 %[[Ctx]], %[[NoAlias]]
35 ; CHECK-NEXT: %[[NOV:[._a-zA-Z0-9]*]] = xor i1 %[[OS1]], true
[all …]
H A Daliasing_parametric_simple_1.ll8 ; CHECK: %[[Cext:[._a-zA-Z0-9]*]] = sext i32 %c to i64
11 ; CHECK: %[[OS:[._a-zA-Z0-9]*]] = or i1 false, %[[Cp1O]]
14 ; CHECK: %[[AMin:[._a-zA-Z0-9]*]] = getelementptr i32, i32* %A, i64 0
15 ; CHECK: %[[BMaxI:[._a-zA-Z0-9]*]] = ptrtoint i32* %[[BMax]] to i64
16 ; CHECK: %[[AMinI:[._a-zA-Z0-9]*]] = ptrtoint i32* %[[AMin]] to i64
20 ; CHECK: %[[AMaxI:[._a-zA-Z0-9]*]] = ptrtoint i32* %[[AMax]] to i64
21 ; CHECK: %[[BMinI:[._a-zA-Z0-9]*]] = ptrtoint i32* %[[BMin]] to i64
23 ; CHECK: %[[NoAlias:[._a-zA-Z0-9]*]] = or i1 %[[BltA]], %[[AltB]]
24 ; CHECK: %[[RTC:[._a-zA-Z0-9]*]] = and i1 true, %[[NoAlias]]
25 ; CHECK: %[[NOV:[._a-zA-Z0-9]*]] = xor i1 %[[OS]], true
[all …]
H A Dsimple_vec_stride_x.ll57 ; CHECK: [[LOAD1:%[a-zA-Z0-9_]+_scalar_]] = load float, float*
58 ; CHECK: [[VEC1:%[a-zA-Z0-9_]+]] = insertelement <4 x float> undef, float [[LOAD1]], i32 0
59 ; CHECK: [[LOAD2:%[a-zA-Z0-9_]+]] = load float, float*
60 ; CHECK: [[VEC2:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC1]], float [[LOAD2]], i32 1
61 ; CHECK: [[LOAD3:%[a-zA-Z0-9_]+]] = load float, float*
62 ; CHECK: [[VEC3:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC2]], float [[LOAD3]], i32 2
63 ; CHECK: [[LOAD4:%[a-zA-Z0-9_]+]] = load float, float*
65 ; CHECK: [[EL1:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 0
67 ; CHECK: [[EL2:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 1
69 ; CHECK: [[EL3:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 2
[all …]
H A Dpointer-type-pointer-type-comparison.ll42 ; CODEGEN-NEXT: %[[Q:[_a-zA-Z0-9]+]] = ptrtoint float* %Q to i64
43 ; CODEGEN-NEXT: %[[P:[_a-zA-Z0-9]+]] = ptrtoint float* %P to i64
44 ; CODEGEN-NEXT: %[[PInc:[_a-zA-Z0-9]+]] = add nsw i64 %[[P]], 1
45 ; CODEGEN-NEXT: %[[CMP:[_a-zA-Z0-9]+]] = icmp sge i64 %[[Q]], %[[PInc]]
46 ; CODEGEN-NEXT: %[[P2:[_a-zA-Z0-9]+]] = ptrtoint float* %P to i64
47 ; CODEGEN-NEXT: %[[Q2:[_a-zA-Z0-9]+]] = ptrtoint float* %Q to i64
48 ; CODEGEN-NEXT: %[[QInc:[_a-zA-Z0-9]+]] = add nsw i64 %[[Q2]], 1
49 ; CODEGEN-NEXT: %[[CMP2:[_a-zA-Z0-9]+]] = icmp sge i64 %[[P2]], %[[QInc]]
50 ; CODEGEN-NEXT: %[[CMP3:[_a-zA-Z0-9]+]] = or i1 %[[CMP]], %[[CMP2]]
H A Dparam_div_div_div_2.ll16 ; IR: %[[A:[.a-zA-Z0-9]*]] = zext i32 %a to i64
17 ; IR-NEXT: %[[B:[.a-zA-Z0-9]*]] = zext i32 %b to i64
18 ; IR-NEXT: %[[R1:[.a-zA-Z0-9]*]] = call i64 @llvm.umax.i64(i64 %[[B]], i64 1)
19 ; IR-NEXT: %[[R2:[.a-zA-Z0-9]*]] = udiv i64 %[[A]], %[[R1]]
20 ; IR-NEXT: %[[C:[.a-zA-Z0-9]*]] = zext i32 %c to i64
21 ; IR-NEXT: %[[D:[.a-zA-Z0-9]*]] = zext i32 %d to i64
22 ; IR-NEXT: %[[R6:[.a-zA-Z0-9]*]] = call i64 @llvm.umax.i64(i64 %[[D]], i64 1)
23 ; IR-NEXT: %[[R7:[.a-zA-Z0-9]*]] = udiv i64 %[[C]], %[[R6]]
24 ; IR-NEXT: %[[R4:[.a-zA-Z0-9]*]] = call i64 @llvm.umax.i64(i64 %[[R7]], i64 1)
25 ; IR-NEXT: %[[R8:[.a-zA-Z0-9]*]] = udiv i64 %[[R2]], %[[R4]]
H A Dsimple_vec_call.ll28 ; CHECK: [[RES1:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW:#[0-9]+]]
29 ; CHECK: [[RES2:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW]]
30 ; CHECK: [[RES3:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW]]
31 ; CHECK: [[RES4:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW]]
32 ; CHECK: [[RES5:%[a-zA-Z0-9_]+]] = insertelement <4 x float> undef, float [[RES1]], i32 0
33 ; CHECK: [[RES6:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[RES5]], float [[RES2]], i32 1
34 ; CHECK: [[RES7:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[RES6]], float [[RES3]], i32 2
35 ; CHECK: [[RES8:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[RES7]], float [[RES4]], i32 3
H A Daliasing_different_pointer_types.ll9 ; CHECK: %[[paBb:[._a-zA-Z0-9]]] = ptrtoint float** %polly.access.B to i64
10 ; CHECK: %[[paAb:[._a-zA-Z0-9]]] = ptrtoint double** %polly.access.A to i64
11 ; CHECK: %[[ALeB:[._a-zA-Z0-9]]] = icmp ule i64 %[[paBb]], %[[paAb]]
14 ; CHECK: %[[paA1b:[._a-zA-Z0-9]]] = ptrtoint double** %polly.access.A1 to i64
15 ; CHECK: %[[paB2b:[._a-zA-Z0-9]]] = ptrtoint float** %polly.access.B2 to i64
16 ; CHECK: %[[A1LeB2:[._a-zA-Z0-9]]] = icmp ule i64 %[[paA1b]], %[[paB2b]]
17 ; CHECK: %[[le1OrLe2:[._a-zA-Z0-9]]] = or i1 %[[ALeB]], %[[A1LeB2]]
18 ; CHECK: %[[orAndTrue:[._a-zA-Z0-9]]] = and i1 true, %[[le1OrLe2]]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Ddecompose-ops.mlir46 // CHECK-SAME: %[[B0:[a-zA-Z0-9]+]]: f32
47 // CHECK-SAME: %[[B1:[a-zA-Z0-9]+]]: f32
48 // CHECK-SAME: %[[B2:[a-zA-Z0-9]+]]: f32
49 // CHECK-SAME: %[[B3:[a-zA-Z0-9]+]]: f32
50 // CHECK-SAME: %[[B4:[a-zA-Z0-9]+]]: f32
51 // CHECK-SAME: %[[B5:[a-zA-Z0-9]+]]: f32):
60 // CHECK-SAME: %[[B6:[a-zA-Z0-9]+]]: f32
61 // CHECK-SAME: %[[B7:[a-zA-Z0-9]+]]: f32
62 // CHECK-SAME: %[[B8:[a-zA-Z0-9]+]]: f32
63 // CHECK-SAME: %[[B9:[a-zA-Z0-9]+]]: f32
[all …]
H A Dtransform-op-split-reduction-by-scaling.mlir9 …// CHECK-SAME: ins(%{{[a-zA-Z0-9]*}}, %{{[a-zA-Z0-9]*}}, %{{[a-zA-Z0-9]*}} : tensor<?x256xf32>, te…
10 // CHECK-SAME: outs(%{{[a-zA-Z0-9]*}} : tensor<?x32x64xf32>) {
14 // CHECK-SAME: ins(%{{[a-zA-Z0-9]*}} : tensor<?x32x64xf32>)
15 // CHECK-SAME: outs(%{{[a-zA-Z0-9]*}} : tensor<?x32xf32>) {
/llvm-project-15.0.7/llvm/test/Assembler/
H A DConstantExprFold.ll41 ; CHECK: @[[A:[a-zA-Z0-9_$"\\.-]+]] = global i64 0
42 ; CHECK: @[[ADD:[a-zA-Z0-9_$"\\.-]+]] = global i64* @A
43 ; CHECK: @[[SUB:[a-zA-Z0-9_$"\\.-]+]] = global i64* @A
44 ; CHECK: @[[MUL:[a-zA-Z0-9_$"\\.-]+]] = global i64* null
45 ; CHECK: @[[AND1:[a-zA-Z0-9_$"\\.-]+]] = global i64* null
46 ; CHECK: @[[AND2:[a-zA-Z0-9_$"\\.-]+]] = global i64* @A
47 ; CHECK: @[[OR:[a-zA-Z0-9_$"\\.-]+]] = global i64 -1
48 ; CHECK: @[[XOR:[a-zA-Z0-9_$"\\.-]+]] = global i64* @A
51 ; CHECK: @[[ICMP_SLT:[a-zA-Z0-9_$"\\.-]+]] = global i1 false
54 ; CHECK: @[[AND3:[a-zA-Z0-9_$"\\.-]+]] = global i64 0
[all …]
H A Dauto_upgrade_nvvm_intrinsics.ll54 ; CHECK-DAG: [[negi:%[a-zA-Z0-9.]+]] = sub i32 0, %a
55 ; CHECK-DAG: [[cmpi:%[a-zA-Z0-9.]+]] = icmp sge i32 %a, 0
59 ; CHECK-DAG: [[negll:%[a-zA-Z0-9.]+]] = sub i64 0, %b
60 ; CHECK-DAG: [[cmpll:%[a-zA-Z0-9.]+]] = icmp sge i64 %b, 0
69 ; CHECK: [[maxi:%[a-zA-Z0-9.]+]] = icmp sge i32 %a1, %a2
73 ; CHECK: [[maxll:%[a-zA-Z0-9.]+]] = icmp sge i64 %b1, %b2
77 ; CHECK: [[maxui:%[a-zA-Z0-9.]+]] = icmp uge i32 %a1, %a2
81 ; CHECK: [[maxull:%[a-zA-Z0-9.]+]] = icmp uge i64 %b1, %b2
85 ; CHECK: [[mini:%[a-zA-Z0-9.]+]] = icmp sle i32 %a1, %a2
89 ; CHECK: [[minll:%[a-zA-Z0-9.]+]] = icmp sle i64 %b1, %b2
[all …]
/llvm-project-15.0.7/polly/test/CodeGen/MemAccess/
H A Dcodegen_simple_md.ll57 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
58 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
59 ; WITHCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]]
60 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
61 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
62 ; WITHCONST: %[[SUM2:[._a-zA-Z0-9]+]] = add nsw i64 %[[SUM1]], 5
66 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
67 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
68 ; WITHOUTCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]]
69 ; WITHOUTCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
[all …]
H A Dcodegen_simple_md_float.ll54 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
55 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
56 ; WITHCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]]
57 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
58 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
59 ; WITHCONST: %[[SUM2:[._a-zA-Z0-9]+]] = add nsw i64 %[[SUM1]], 5
63 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
64 …[ 0, %polly.loop_preheader{{[0-9]*}} ], [ %polly.indvar_next{{[0-9]*}}, %polly.{{[._a-zA-Z0-9]*}} ]
65 ; WITHOUTCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]]
66 ; WITHOUTCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/ControlFlow/
H A Dcanonicalize.mlir146 // CHECK-SAME: %[[FLAG:[a-zA-Z0-9_]+]]
147 // CHECK-SAME: %[[CASE_OPERAND_0:[a-zA-Z0-9_]+]]
165 // CHECK-SAME: %[[FLAG:[a-zA-Z0-9_]+]]
166 // CHECK-SAME: %[[CASE_OPERAND_0:[a-zA-Z0-9_]+]]
167 // CHECK-SAME: %[[CASE_OPERAND_1:[a-zA-Z0-9_]+]]
190 // CHECK-SAME: %[[CASE_OPERAND_0:[a-zA-Z0-9_]+]]
191 // CHECK-SAME: %[[CASE_OPERAND_1:[a-zA-Z0-9_]+]]
242 // CHECK-SAME: %[[FLAG:[a-zA-Z0-9_]+]]
285 // CHECK-SAME: %[[FLAG:[a-zA-Z0-9_]+]]
321 // CHECK-SAME: %[[FLAG:[a-zA-Z0-9_]+]]
[all …]
/llvm-project-15.0.7/mlir/test/Interfaces/TilingInterface/
H A Dtile-using-interface.mlir13 // CHECK-SAME: %[[ARG0:[a-zA-Z0-9]+]]: tensor<?x?xf32>
14 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]: tensor<?x?xf32>
23 // CHECK: %[[OUTER:[a-zA-Z0-9]+]] = scf.for %[[IV0:[a-zA-Z0-9]+]] = %[[C0]] to %[[M]] step %…
26 // CHECK: %[[INNER:[a-zA-Z0-9]+]] = scf.for %[[IV1:[a-zA-Z0-9]+]] = %[[C0]] to %[[N]] step…
114 // CHECK: %[[OUTER:[a-zA-Z0-9]+]]:2 = scf.for %[[IV0:[a-zA-Z0-9]+]] = %[[C0]] to %[[C128]] s…
115 // CHECK-SAME: iter_args(%[[ARG1:[a-zA-Z0-9]+]] = %[[INIT0]], %[[ARG2:[a-zA-Z0-9]+]] = %[[INI…
117 // CHECK: %[[INNER:[a-zA-Z0-9]+]]:2 = scf.for %[[IV1:[a-zA-Z0-9]+]] = %[[C0]] to %[[C300]]…
118 // CHECK-SAME: iter_args(%[[ARG3:[a-zA-Z0-9]+]] = %[[ARG1]], %[[ARG4:[a-zA-Z0-9]+]] = %[[AR…
254 // CHECK: %[[OUTER:[a-zA-Z0-9]+]] = scf.for %[[IV0:[a-zA-Z0-9]+]] = %[[C0]] to %[[N]] step %…
257 // CHECK: %[[INNER1:[a-zA-Z0-9]+]] = scf.for %[[IV1:[a-zA-Z0-9]+]] = %[[C0]] to %[[K]] ste…
[all …]
H A Dtile-and-fuse-using-interface.mlir17 // CHECK-SAME: %[[ARG0:[a-zA-Z0-9]+]]: tensor<?x?xf32>
18 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]: tensor<?x?xf32>)
20 // CHECK: scf.for %[[IV0:[a-zA-Z0-9]+]] =
22 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] =
65 // CHECK: scf.for %[[IV0:[a-zA-Z0-9]+]] =
67 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] =
115 // CHECK: scf.for %[[IV:[a-zA-Z0-9]+]] =
168 // CHECK: scf.for %[[IV0:[a-zA-Z0-9]+]] =
170 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] =
215 // CHECK: scf.for %[[IV0:[a-zA-Z0-9]+]] =
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Dliterals.mm19 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8*
20 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8*]
21 // CHECK: [[TMPX:%[a-zA-Z0-9.]+]] = alloca %
22 // CHECK: [[TMPY:%[a-zA-Z0-9.]+]] = alloca %
27 …// CHECK: [[ELEMENT0:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[OBJECTS]], …
35 …// CHECK: [[ELEMENT1:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[OBJECTS]], …
39 …// CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke noundef i8* @_ZNK1YcvP11objc_objectEv{{.*}} [ "clang…
74 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8*
75 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8*]
80 …// CHECK: [[ELEMENT0:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[OBJECTS]], …
[all …]
/llvm-project-15.0.7/llvm/test/Instrumentation/SanitizerCoverage/
H A Dopaque-ptr.ll5 ; CHECK: @[[__SANCOV_LOWEST_STACK:[a-zA-Z0-9_$"\\.-]+]] = external thread_local(initialexec) global…
6 ; CHECK: @[[__SANCOV_GEN_:[a-zA-Z0-9_$"\\.-]+]] = private global [1 x i32] zeroinitializer, section…
7 ; CHECK: @[[__START___SANCOV_GUARDS:[a-zA-Z0-9_$"\\.-]+]] = extern_weak hidden global i32
8 ; CHECK: @[[__STOP___SANCOV_GUARDS:[a-zA-Z0-9_$"\\.-]+]] = extern_weak hidden global i32
9 ; CHECK: @[[LLVM_GLOBAL_CTORS:[a-zA-Z0-9_$"\\.-]+]] = appending global [1 x { i32, ptr, ptr }] [{ i…
10 ; CHECK: @[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [1 x ptr] [ptr @__sancov_ge…
/llvm-project-15.0.7/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
H A Dsplit-gep.ll42 … float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
43 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 32
63 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6…
88 …TR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6…
90 …TR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6…
108 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6…
123 …ECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2…
142 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 8
152 ; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j
170 …PTR:%[a-zA-Z0-9]+]] = getelementptr [1024 x %struct.Packed], [1024 x %struct.Packed]* %s, i64 0, i…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc64-toc.ll65 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
67 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
69 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
71 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
H A Dtail-dup-branch-to-fallthrough.ll16 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
18 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
20 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
22 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
24 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
26 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
28 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
H A Dbrcond.ll9 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
24 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
39 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
54 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
69 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
84 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
99 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
114 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
129 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
144 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Tensor/
H A Dresolve-shaped-type-result-dims.mlir45 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
46 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
47 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]+]]: index
62 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
77 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
92 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
107 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
124 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
125 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9_]+]]: index
142 // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-gep-opt.ll43 ; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
44 ; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]]
55 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
96 ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528
101 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, {{.*}}, i64 532
105 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, {{.*}}, i64 528
108 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr
133 ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, 88
136 ; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 88
155 ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, -40
[all …]

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