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Searched refs:XLenVT (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4555 DAG.getNode(ISD::ADD, DL, XLenVT, Idx, DAG.getConstant(1, DL, XLenVT)); in lowerINSERT_VECTOR_ELT()
4987 XLenVT); in LowerINTRINSIC_W_CHAIN()
5086 XLenVT); in LowerINTRINSIC_VOID()
6553 if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) { in lowerMaskedGather()
6655 if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) { in lowerMaskedScatter()
6699 DAG.getNode(ISD::SHL, DL, XLenVT, RM, DAG.getConstant(2, DL, XLenVT)); in lowerGET_ROUNDING()
8532 if (VT == XLenVT) in performFP_TO_INTCombine()
8559 if (DstVT != XLenVT) in performFP_TO_INT_SATCombine()
10394 LocVT = XLenVT; in CC_RISCV()
10456 LocVT = XLenVT; in CC_RISCV()
[all …]
H A DRISCVInstrInfoVVLPatterns.td29 SDTCisVT<4, XLenVT>]>;
35 SDTCisVT<3, XLenVT>]>;
41 SDTCisVT<4, XLenVT>]>;
106 SDTCisVT<5, XLenVT>]>;
179 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, XLenVT>
198 def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>;
857 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1),
882 (op1 (SplatPat XLenVT:$rs1),
1203 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>;
1207 $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>;
[all …]
H A DRISCVInstrInfoZb.td67 def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
97 def BCLRMask : ImmLeaf<XLenVT, [{
104 def BSETINVMask : ImmLeaf<XLenVT, [{
237 def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
1146 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 11)),
1148 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 19)),
1150 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 13)),
1152 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 21)),
1154 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 37)),
1156 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 25)),
[all …]
H A DRISCVInstrInfoC.td21 def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
51 def simm6nonzero : Operand<XLenVT>,
64 def immzero : Operand<XLenVT>,
81 def c_lui_imm : Operand<XLenVT>,
98 def uimm7_lsb00 : Operand<XLenVT>,
112 def uimm8_lsb00 : Operand<XLenVT>,
126 def uimm8_lsb000 : Operand<XLenVT>,
157 def uimm9_lsb000 : Operand<XLenVT>,
173 ImmLeaf<XLenVT,
[all …]
H A DRISCVInstrInfoVSDPatterns.td25 (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
415 (vti.Mask true_mask), (XLenVT srcvalue))),
418 (vti.Mask true_mask), (XLenVT srcvalue)))),
423 (vti.Mask true_mask), (XLenVT srcvalue))),
426 (vti.Mask true_mask), (XLenVT srcvalue)))),
431 (vti.Mask true_mask), (XLenVT srcvalue))),
445 (vti.Mask true_mask), (XLenVT srcvalue)))),
451 (vti.Mask true_mask), (XLenVT srcvalue)))),
472 (vti.Mask true_mask), (XLenVT srcvalue))),
508 (vti.Mask true_mask), (XLenVT srcvalue)),
[all …]
H A DRISCVInstrInfo.td150 def fencearg : Operand<XLenVT> {
164 def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
184 def uimm2 : Operand<XLenVT> {
191 def uimm3 : Operand<XLenVT> {
198 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
219 def uimm7 : Operand<XLenVT> {
226 def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
348 def csr_sysreg : Operand<XLenVT> {
357 def ixlenimm : Operand<XLenVT>;
366 def simm12_plus1 : ImmLeaf<XLenVT,
[all …]
H A DRISCVISelDAGToDAG.cpp275 MVT XLenVT = Subtarget->getXLenVT(); in addVectorLoadStoreOperands() local
343 MVT XLenVT = Subtarget->getXLenVT(); in selectVLSEGFF() local
521 MVT XLenVT = Subtarget->getXLenVT(); in selectVSETVLI() local
549 SmallVector<EVT, 2> VTs = {XLenVT}; in selectVSETVLI()
556 VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT); in selectVSETVLI()
593 MVT XLenVT = Subtarget->getXLenVT(); in Select() local
600 if (VT == XLenVT && ConstNode->isZero()) { in Select()
1004 if (Src2.getValueType() != XLenVT) in Select()
1063 if (Src2.getValueType() != XLenVT) in Select()
2282 MVT XLenVT = Subtarget.getXLenVT(); in selectVSplatSimmHelper() local
[all …]
H A DRISCVRegisterInfo.td118 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
126 def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
137 def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> {
141 def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X0)> {
145 def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X0, X2)> {
153 def GPRJALR : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, (sequence "X%u", 0, 5))> {
157 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
168 def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
176 def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
465 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
H A DRISCVInstrInfoZicbo.td19 def simm12_lsb00000 : Operand<XLenVT>,
20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
H A DRISCVSubtarget.h103 MVT XLenVT = MVT::i32; variable
197 MVT getXLenVT() const { return XLenVT; } in getXLenVT()
H A DRISCVInstrInfoVPseudos.td35 def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
159 def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
164 def VLMax : OutPatFrag<(ops), (XLenVT -1)>;
195 string ScalarSuffix = !cond(!eq(Scal, XLenVT) : "X",
3036 VLOpFrag, (XLenVT timm:$policy))),
3196 VLOpFrag, (XLenVT timm:$policy))),
3273 VLOpFrag, (XLenVT timm:$policy))),
3316 VLOpFrag, (XLenVT timm:$policy))),
3365 VLOpFrag, (XLenVT timm:$policy))),
3377 def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name)
[all …]
H A DRISCVSubtarget.cpp81 XLenVT = MVT::i64; in initializeSubtargetDependencies()
H A DRISCVInstrInfoF.td26 : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisFP<1>,
27 SDTCisVT<2, XLenVT>]>;
139 def frmarg : Operand<XLenVT> {
H A DRISCVInstrInfoZfh.td19 : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>;
21 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>;
H A DRISCVInstrInfoV.td27 class VTypeIOp<int VTypeINum> : Operand<XLenVT> {
53 def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
71 def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
82 def simm5_plus1_nonzero : ImmLeaf<XLenVT,
H A DRISCVInstrInfoA.td47 ValueType vt = XLenVT> {
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp360 const MVT XLenVT = MVT::i32; in LowerFormalArguments() local
395 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); in LowerFormalArguments()
509 MVT XLenVT = MVT::i32; in LowerCall() local
546 SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); in LowerCall()
1237 MVT XLenVT = MVT::i32; in LowerGlobalTLSAddress() local
1260 DAG.getConstant(Offset, DL, XLenVT)); in LowerGlobalTLSAddress()