Home
last modified time | relevance | path

Searched refs:XD (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Ddevirtualize-virtual-function-calls.cpp44 struct XD { D d; }; struct
48 void fd(D d, XD xd, D *p) { in fd()
80 XD().d.f(); in fd()
83 D XD::*mp; in fd()
/llvm-project-15.0.7/llvm/test/TableGen/
H A Ddefmclass.td4 class XD { bits<4> Prefix = 11; }
9 def xd : XD;
31 defm SS : R, M, XD;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrSNP.td26 XD, Requires<[In64BitMode]>;
30 XD, Requires<[Not64BitMode]>;
34 def RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, XD,
H A DX86InstrFormats.td143 def XD : Prefix<3>;
213 class T_MAP5XD : T_MAP5 { Prefix OpPrefix = XD; } // 0xF2
218 class T_MAP6XD : T_MAP6 { Prefix OpPrefix = XD; }
222 class XD : TB { Prefix OpPrefix = XD; }
226 class T8XD : T8 { Prefix OpPrefix = XD; }
230 class TAXD : TA { Prefix OpPrefix = XD; }
623 // SDI - SSE2 instructions with XD prefix.
689 // S3DI - SSE3 instructions with XD prefix.
826 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, XD,
847 class AVX512XDIi8Base : XD {
[all …]
H A DX86InstrSSE.td280 SSEPackedDouble>, XD;
920 XD, VEX, VEX_LIG;
1073 SSEPackedDouble>, XD;
1076 SSEPackedDouble>, XD, REX_W;
1088 XD, VEX_4V, VEX_LIG;
1091 XD, VEX_4V, VEX_LIG, VEX_W, SIMD_EXC;
1102 XD;
1105 XD, REX_W, SIMD_EXC;
1169 XD, REX_W;
1334 XD, Requires<[UseSSE2]>,
[all …]
H A DX86InstrAVX512.td2889 VEX, XD;
2893 VEX, XD, VEX_W;
3653 XD, EVEX_CD8<8, CD8VF>;
3659 XD, VEX_W, EVEX_CD8<16, CD8VF>;
4546 []>, XD, EVEX_4V, VEX_LIG, VEX_W,
4556 []>, EVEX_K, XD, EVEX_4V, VEX_LIG,
7628 XD, EVEX_CD8<64, CD8VT1>;
7634 XD, EVEX_CD8<64, CD8VT1>;
7809 "{l}">, XD, EVEX_CD8<64, CD8VT1>;
7822 "{l}">, XD, EVEX_CD8<64, CD8VT1>;
[all …]
H A DX86InstrInfo.td2850 XD, Requires<[HasWAITPKG]>;
2983 [(int_x86_xsusldtrk)]>, XD;
2985 [(int_x86_xresldtrk)]>, XD;
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp197 else if (OpPrefix == X86Local::XD) in insnContext()
211 else if (OpPrefix == X86Local::XD) in insnContext()
225 else if (OpPrefix == X86Local::XD) in insnContext()
237 else if (OpPrefix == X86Local::XD) in insnContext()
254 else if (OpPrefix == X86Local::XD) in insnContext()
266 else if (OpPrefix == X86Local::XD) in insnContext()
283 else if (OpPrefix == X86Local::XD) in insnContext()
299 else if (HasVEX_L && OpPrefix == X86Local::XD) in insnContext()
309 else if (OpPrefix == X86Local::XD) in insnContext()
340 else if (OpPrefix == X86Local::XD) in insnContext()
[all …]
H A DX86RecognizableInstr.h141 PD = 1, XS = 2, XD = 3, PS = 4 enumerator
/llvm-project-15.0.7/clang/test/Modules/Inputs/declare-use/
H A Dmodule.map15 module XD {
/llvm-project-15.0.7/clang/test/Parser/
H A Dcxx1z-class-template-argument-deduction.cpp27 template<template<typename> typename = A> struct XD {}; struct
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86IntelInstPrinter.cpp88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
198 } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) { in printVecCompareInstr()
H A DX86ATTInstPrinter.cpp105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
208 } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) { in printVecCompareInstr()
H A DX86MCCodeEmitter.cpp775 case X86II::XD: in emitVEXOpcodePrefix()
1273 case X86II::XD: // F2 in emitOpcodePrefix()
H A DX86BaseInfo.h791 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift, enumerator
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td77 def XD : ExtInfo_rr<DExt, GPR, FPR64>;
87 defvar XDINX = [XD, XD_INX, XD_IN32X];
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td494 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>;
H A DAArch64SchedExynosM3.td563 def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>;
H A DAArch64SchedFalkorDetails.td1149 def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WS|XD|XDHigh)r$")>;
/llvm-project-15.0.7/llvm/docs/TableGen/
H A DProgRef.rst1084 class XD {
1100 defm SS : R, XD; // First multiclass R, then regular class XD.