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Searched refs:Writeback (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGCall.h263 struct Writeback { struct
305 Writeback writeback = {srcLV, temporary, toUse}; in addWriteback()
311 typedef llvm::iterator_range<SmallVectorImpl<Writeback>::const_iterator>
339 SmallVector<Writeback, 1> Writebacks;
H A DCGCall.cpp3826 const CallArgList::Writeback &writeback) { in emitWriteback()
/llvm-project-15.0.7/clang/test/SemaObjCXX/
H A Darc-overloading.mm57 // Writeback conversion
72 // Writeback conversion vs. no conversion
88 // Writeback conversion vs. other conversion.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp642 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback. in CreateLoadStoreMulti() local
650 Writeback = false; in CreateLoadStoreMulti()
688 Writeback = false; in CreateLoadStoreMulti()
795 if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill) in CreateLoadStoreMulti()
800 if (Writeback) { in CreateLoadStoreMulti()
H A DARMInstrVFP.td244 let Inst{21} = 1; // Writeback
253 let Inst{21} = 1; // Writeback
276 let Inst{21} = 1; // Writeback
289 let Inst{21} = 1; // Writeback
377 let Inst{21} = 1; // Writeback
384 let Inst{21} = 1; // Writeback
H A DARMInstrThumb.td834 // Writeback version is just a pseudo, as there's no encoding difference.
835 // Writeback happens iff the base register is not in the destination register
H A DARMInstrThumb2.td1999 let Inst{21} = 1; // Writeback
2029 let Inst{21} = 1; // Writeback
2071 let Inst{21} = 1; // Writeback
2107 let Inst{21} = 1; // Writeback
H A DARMInstrInfo.td3467 let Inst{21} = 1; // Writeback
3487 let Inst{21} = 1; // Writeback
3507 let Inst{21} = 1; // Writeback
3527 let Inst{21} = 1; // Writeback
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp233 bool Writeback = true; in printInst() local
237 Writeback = false; in printInst()
245 if (Writeback) in printInst()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-thumbv7.txt46 # Writeback is not allowed is Rn is in the target register list.
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Duserstack.ll225 ; Writeback to memory.
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb-diagnostics.s399 @ Writeback store writing to same register as value
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp654 template <bool Writeback>
6664 template <bool Writeback>
6695 if (Writeback) { in DecodeVSTRVLDR_SYSREG()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp665 bool Load, bool ARMMode, bool Writeback);
7571 bool Load, bool ARMMode, bool Writeback) { in validateLDRDSTRD() argument
7572 unsigned RtIndex = Load || !Writeback ? 0 : 1; in validateLDRDSTRD()
7607 if (Writeback) { in validateLDRDSTRD()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_mve.td313 // Writeback without predication