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Searched refs:WriteRes (Results 1 – 25 of 52) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFive7.td42 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
43 def : WriteRes<WriteJal, [SiFive7PipeB]>;
44 def : WriteRes<WriteJalr, [SiFive7PipeB]>;
74 def : WriteRes<WriteSTB, [SiFive7PipeA]>;
75 def : WriteRes<WriteSTH, [SiFive7PipeA]>;
76 def : WriteRes<WriteSTW, [SiFive7PipeA]>;
77 def : WriteRes<WriteSTD, [SiFive7PipeA]>;
82 def : WriteRes<WriteLDB, [SiFive7PipeA]>;
83 def : WriteRes<WriteLDH, [SiFive7PipeA]>;
84 def : WriteRes<WriteLDW, [SiFive7PipeA]>;
[all …]
H A DRISCVSchedRocket.td51 def : WriteRes<WriteJmp, [RocketUnitB]>;
52 def : WriteRes<WriteJal, [RocketUnitB]>;
53 def : WriteRes<WriteJalr, [RocketUnitB]>;
82 def : WriteRes<WriteSTB, [RocketUnitMem]>;
83 def : WriteRes<WriteSTH, [RocketUnitMem]>;
84 def : WriteRes<WriteSTW, [RocketUnitMem]>;
85 def : WriteRes<WriteSTD, [RocketUnitMem]>;
90 def : WriteRes<WriteLDB, [RocketUnitMem]>;
91 def : WriteRes<WriteLDH, [RocketUnitMem]>;
174 def : WriteRes<WriteCSR, []>;
[all …]
H A DRISCVScheduleV.td497 def : WriteRes<WriteVLDE8, []>;
501 def : WriteRes<WriteVSTE8, []>;
505 def : WriteRes<WriteVLDM, []>;
506 def : WriteRes<WriteVSTM, []>;
507 def : WriteRes<WriteVLDS8, []>;
511 def : WriteRes<WriteVSTS8, []>;
551 def : WriteRes<WriteVST1R, []>;
552 def : WriteRes<WriteVST2R, []>;
553 def : WriteRes<WriteVST4R, []>;
554 def : WriteRes<WriteVST8R, []>;
[all …]
H A DRISCVScheduleB.td187 def : WriteRes<WriteCLZ, []>;
189 def : WriteRes<WriteCTZ, []>;
191 def : WriteRes<WriteCPOP, []>;
193 def : WriteRes<WriteREV8, []>;
194 def : WriteRes<WriteORCB, []>;
245 def : WriteRes<WriteBFP, []>;
263 def : WriteRes<WriteORC, []>;
264 def : WriteRes<WriteREV, []>;
271 def : WriteRes<WriteSHFL, []>;
279 def : WriteRes<WritePACK, []>;
[all …]
H A DRISCVSchedule.td187 def : WriteRes<WriteFALU16, []>;
188 def : WriteRes<WriteFClass16, []>;
197 def : WriteRes<WriteFDiv16, []>;
198 def : WriteRes<WriteFCmp16, []>;
199 def : WriteRes<WriteFLD16, []>;
200 def : WriteRes<WriteFMA16, []>;
201 def : WriteRes<WriteFMinMax16, []>;
202 def : WriteRes<WriteFMul16, []>;
205 def : WriteRes<WriteFSGNJ16, []>;
206 def : WriteRes<WriteFST16, []>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td71 def : WriteRes<WriteImm, []> { let Unsupported = 1; }
72 def : WriteRes<WriteI, []> { let Unsupported = 1; }
73 def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
74 def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
75 def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
76 def : WriteRes<WriteIS, []> { let Unsupported = 1; }
77 def : WriteRes<WriteID32, []> { let Unsupported = 1; }
78 def : WriteRes<WriteID64, []> { let Unsupported = 1; }
79 def : WriteRes<WriteIM32, []> { let Unsupported = 1; }
80 def : WriteRes<WriteIM64, []> { let Unsupported = 1; }
[all …]
H A DAArch64SchedKryo.td68 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
70 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
72 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
75 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
77 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
89 def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]>
95 def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]>
97 def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]>
104 def : WriteRes<WriteSys, []> { let Latency = 1; }
105 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
[all …]
H A DAArch64SchedThunderX.td60 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
65 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
71 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
76 def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
87 def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
127 def : WriteRes<WriteVST, [THXT8XUnitLdSt]>;
143 def : WriteRes<WriteBr, [THXT8XUnitBr]>;
145 def : WriteRes<WriteBrReg, [THXT8XUnitBr]>;
148 def : WriteRes<WriteSys, [THXT8XUnitBr]>;
149 def : WriteRes<WriteBarrier, [THXT8XUnitBr]>;
[all …]
H A DAArch64SchedA53.td61 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
65 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
85 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
99 def : WriteRes<WriteAdr, []> { let Latency = 0; }
116 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
119 def : WriteRes<WriteBr, [A53UnitB]>;
120 def : WriteRes<WriteBrReg, [A53UnitB]>;
121 def : WriteRes<WriteSys, [A53UnitB]>;
122 def : WriteRes<WriteBarrier, [A53UnitB]>;
[all …]
H A DAArch64SchedA55.td78 def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
81 def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
86 def : WriteRes<WriteLD, [CortexA55UnitLd]> { let Latency = 3; }
93 def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
117 def : WriteRes<WriteAdr, []> { let Latency = 0; }
138 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
141 def : WriteRes<WriteBr, [CortexA55UnitB]>;
142 def : WriteRes<WriteBrReg, [CortexA55UnitB]>;
143 def : WriteRes<WriteSys, [CortexA55UnitB]>;
144 def : WriteRes<WriteBarrier, [CortexA55UnitB]>;
[all …]
H A DAArch64SchedTSV110.td64 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
66 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
74 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
85 def : WriteRes<WriteF, [TSV110UnitF]> { let Latency = 2; }
86 def : WriteRes<WriteFCmp, [TSV110UnitF]> { let Latency = 3; }
88 def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
90 def : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; }
103 def : WriteRes<WriteSys, []> { let Latency = 1; }
104 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
105 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedCyclone.td134 def : WriteRes<WriteImm, [CyUnitI]>;
153 def : WriteRes<WriteI, [CyUnitI]>;
159 def : WriteRes<WriteISReg, [CyUnitIS]> {
167 def : WriteRes<WriteIEReg, [CyUnitIS]> {
174 def : WriteRes<WriteIS, [CyUnitIS]>;
195 def : WriteRes<WriteIM32, [CyUnitIM]> {
199 def : WriteRes<WriteIM64, [CyUnitIM]> {
227 def : WriteRes<WriteLD, [CyUnitLS]> {
237 def : WriteRes<WriteST, [CyUnitLS]> {
269 def : WriteRes<WriteAdr, [CyUnitI]>;
[all …]
H A DAArch64SchedAmpere1.td598 def : WriteRes<WriteID32, [Ampere1UnitBS]> {
601 def : WriteRes<WriteID64, [Ampere1UnitBS]> {
604 def : WriteRes<WriteIM32, [Ampere1UnitBS]> {
607 def : WriteRes<WriteIM64, [Ampere1UnitBS]> {
610 def : WriteRes<WriteBr, [Ampere1UnitA]>;
612 def : WriteRes<WriteLD, [Ampere1UnitL]> {
615 def : WriteRes<WriteST, [Ampere1UnitS]> {
622 def : WriteRes<WriteAdr, [Ampere1UnitAB]>;
631 def : WriteRes<WriteF, [Ampere1UnitXY]> {
634 def : WriteRes<WriteFCmp, [Ampere1UnitX]> {
[all …]
H A DAArch64SchedExynosM3.td208 def : WriteRes<WriteID32, [M3UnitC,
211 def : WriteRes<WriteID64, [M3UnitC,
214 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
215 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
227 def : WriteRes<WriteLDHi, []> { let Latency = 4;
253 def : WriteRes<WriteVST, [M3UnitS,
258 def : WriteRes<WriteVd, [M3UnitNALU]> { let Latency = 3; }
262 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
263 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
264 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td67 def : WriteRes<SchedRW, ExePorts> {
89 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
90 def : WriteRes<WriteZero, []>;
140 def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
156 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
188 def : WriteRes<WriteFStore, [SLM_MEC_RSV]>;
189 def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>;
190 def : WriteRes<WriteFStoreY, [SLM_MEC_RSV]>;
412 def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>;
460 def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
[all …]
H A DX86ScheduleAtom.td63 def : WriteRes<SchedRW, RRPorts> {
70 def : WriteRes<SchedRW.Folded, RMPorts> {
78 def : WriteRes<WriteRMW, [AtomPort0]>;
122 def : WriteRes<WriteSETCC, [AtomPort01]>;
139 def : WriteRes<WriteLEA, [AtomPort1]>;
171 def : WriteRes<WriteLoad, [AtomPort0]>;
172 def : WriteRes<WriteStore, [AtomPort0]>;
173 def : WriteRes<WriteStoreNT, [AtomPort0]>;
174 def : WriteRes<WriteMove, [AtomPort01]>;
185 def : WriteRes<WriteZero, []>;
[all …]
H A DX86SchedSandyBridge.td91 def : WriteRes<SchedRW, ExePorts> {
108 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
113 def : WriteRes<WriteMove, [SBPort015]>;
120 def : WriteRes<WriteZero, []>;
144 def : WriteRes<WriteIMulHLd, []> {
196 def : WriteRes<WriteLEA, [SBPort01]>;
487 def : WriteRes<WritePCmpIStrM, [SBPort0]> {
509 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
548 def : WriteRes<WriteAESIMC, [SBPort5]> {
569 def : WriteRes<WriteCLMul, [SBPort015]> {
[all …]
H A DX86SchedSkylakeClient.td95 def : WriteRes<SchedRW, ExePorts> {
112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
133 def : WriteRes<WriteIMulHLd, []> {
167 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
217 def : WriteRes<WriteZero, []>;
425 def : WriteRes<WriteVecInsert, [SKLPort5]> {
490 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
514 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
578 def : WriteRes<WriteCLMul, [SKLPort5]> {
603 def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
[all …]
H A DX86SchedBroadwell.td96 def : WriteRes<SchedRW, ExePorts> {
113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
128 def : WriteRes<WriteZero, []>;
153 def : WriteRes<WriteIMulHLd, []> {
184 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
201 def : WriteRes<WriteLEA, [BWPort15]>;
486 def : WriteRes<WriteVecInsert, [BWPort5]> {
508 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
532 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
608 def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
[all …]
H A DX86ScheduleBtVer2.td126 def : WriteRes<SchedRW, ExePorts> {
146 def : WriteRes<SchedRW, ExePorts> {
166 def : WriteRes<SchedRW, ExePorts> {
232 def : WriteRes<WriteLAHFSAHF, [JALU01]>;
242 def : WriteRes<WriteLEA, [JALU01]>;
276 def : WriteRes<WriteStore, [JSAGU]>;
277 def : WriteRes<WriteStoreNT, [JSAGU]>;
278 def : WriteRes<WriteMove, [JALU01]>;
283 def : WriteRes<WriteSTMXCSR, [JSAGU]>;
293 def : WriteRes<WriteZero, []>;
[all …]
H A DX86SchedHaswell.td101 def : WriteRes<SchedRW, ExePorts> {
118 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
130 def : WriteRes<WriteZero, []>;
155 def : WriteRes<WriteIMulHLd, []> {
203 def : WriteRes<WriteLEA, [HWPort15]>;
485 def : WriteRes<WriteVecInsert, [HWPort5]> {
508 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
532 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
562 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
573 def : WriteRes<WriteAESIMC, [HWPort5]> {
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td72 def : WriteRes<WriteMUL16, [M7UnitMAC]>;
73 def : WriteRes<WriteMUL32, [M7UnitMAC]>;
88 def : WriteRes<WriteDIV, [M7UnitALU]> {
155 def : WriteRes<WriteVLD1, []>;
156 def : WriteRes<WriteVLD2, []>;
157 def : WriteRes<WriteVLD3, []>;
158 def : WriteRes<WriteVLD4, []>;
159 def : WriteRes<WriteVST1, []>;
160 def : WriteRes<WriteVST2, []>;
161 def : WriteRes<WriteVST3, []>;
[all …]
H A DARMScheduleR52.td74 def : WriteRes<WriteDIV, [R52UnitDiv]> {
79 def : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; }
108 def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
113 def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
122 def : WriteRes<WriteVST1, []>;
123 def : WriteRes<WriteVST2, []>;
124 def : WriteRes<WriteVST3, []>;
125 def : WriteRes<WriteVST4, []>;
719 def : WriteRes<WriteVLD2, [R52UnitLd]> {
725 def : WriteRes<WriteVLD3, [R52UnitLd]> {
[all …]
H A DARMScheduleM4.td37 class M4UnitL1<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 1; }
38 class M4UnitL2<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 2; }
39 class M4UnitL3<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 3; }
40 class M4UnitL14<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 14; }
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }

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