Lines Matching refs:WriteRes

42 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
43 def : WriteRes<WriteJal, [SiFive7PipeB]>;
44 def : WriteRes<WriteJalr, [SiFive7PipeB]>;
45 def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
49 def : WriteRes<WriteIALU, [SiFive7PipeAB]>;
50 def : WriteRes<WriteIALU32, [SiFive7PipeAB]>;
51 def : WriteRes<WriteShiftImm, [SiFive7PipeAB]>;
52 def : WriteRes<WriteShiftImm32, [SiFive7PipeAB]>;
53 def : WriteRes<WriteShiftReg, [SiFive7PipeAB]>;
54 def : WriteRes<WriteShiftReg32, [SiFive7PipeAB]>;
59 def : WriteRes<WriteIMul, [SiFive7PipeB]>;
60 def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
64 def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
68 def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
74 def : WriteRes<WriteSTB, [SiFive7PipeA]>;
75 def : WriteRes<WriteSTH, [SiFive7PipeA]>;
76 def : WriteRes<WriteSTW, [SiFive7PipeA]>;
77 def : WriteRes<WriteSTD, [SiFive7PipeA]>;
78 def : WriteRes<WriteFST32, [SiFive7PipeA]>;
79 def : WriteRes<WriteFST64, [SiFive7PipeA]>;
82 def : WriteRes<WriteLDB, [SiFive7PipeA]>;
83 def : WriteRes<WriteLDH, [SiFive7PipeA]>;
84 def : WriteRes<WriteLDW, [SiFive7PipeA]>;
85 def : WriteRes<WriteLDWU, [SiFive7PipeA]>;
86 def : WriteRes<WriteLDD, [SiFive7PipeA]>;
90 def : WriteRes<WriteFLD32, [SiFive7PipeA]>;
91 def : WriteRes<WriteFLD64, [SiFive7PipeA]>;
95 def : WriteRes<WriteAtomicSTW, [SiFive7PipeA]>;
96 def : WriteRes<WriteAtomicSTD, [SiFive7PipeA]>;
99 def : WriteRes<WriteAtomicW, [SiFive7PipeA]>;
100 def : WriteRes<WriteAtomicD, [SiFive7PipeA]>;
101 def : WriteRes<WriteAtomicLDW, [SiFive7PipeA]>;
102 def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>;
107 def : WriteRes<WriteFALU32, [SiFive7PipeB]>;
108 def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
109 def : WriteRes<WriteFMA32, [SiFive7PipeB]>;
112 def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>;
113 def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>;
116 def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
118 def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
123 def : WriteRes<WriteFALU64, [SiFive7PipeB]>;
124 def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
125 def : WriteRes<WriteFMA64, [SiFive7PipeB]>;
128 def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>;
129 def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>;
132 def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
134 def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
139 def : WriteRes<WriteFCvtI32ToF32, [SiFive7PipeB]>;
140 def : WriteRes<WriteFCvtI32ToF64, [SiFive7PipeB]>;
141 def : WriteRes<WriteFCvtI64ToF32, [SiFive7PipeB]>;
142 def : WriteRes<WriteFCvtI64ToF64, [SiFive7PipeB]>;
143 def : WriteRes<WriteFCvtF32ToI32, [SiFive7PipeB]>;
144 def : WriteRes<WriteFCvtF32ToI64, [SiFive7PipeB]>;
145 def : WriteRes<WriteFCvtF32ToF64, [SiFive7PipeB]>;
146 def : WriteRes<WriteFCvtF64ToI32, [SiFive7PipeB]>;
147 def : WriteRes<WriteFCvtF64ToI64, [SiFive7PipeB]>;
148 def : WriteRes<WriteFCvtF64ToF32, [SiFive7PipeB]>;
150 def : WriteRes<WriteFClass32, [SiFive7PipeB]>;
151 def : WriteRes<WriteFClass64, [SiFive7PipeB]>;
152 def : WriteRes<WriteFCmp32, [SiFive7PipeB]>;
153 def : WriteRes<WriteFCmp64, [SiFive7PipeB]>;
154 def : WriteRes<WriteFMovI32ToF32, [SiFive7PipeB]>;
155 def : WriteRes<WriteFMovF32ToI32, [SiFive7PipeB]>;
156 def : WriteRes<WriteFMovI64ToF64, [SiFive7PipeB]>;
157 def : WriteRes<WriteFMovF64ToI64, [SiFive7PipeB]>;
161 def : WriteRes<WriteCSR, [SiFive7PipeB]>;
162 def : WriteRes<WriteNop, []>;