| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | LowerMatrixIntrinsics.cpp | 216 SmallVector<Value *, 16> Vectors; member in __anon8ba1aee70111::LowerMatrixIntrinsics::MatrixTy
224 MatrixTy(ArrayRef<Value *> Vectors) in MatrixTy() argument
225 : Vectors(Vectors.begin(), Vectors.end()), in MatrixTy()
239 return Vectors[i]; in getColumn()
243 return Vectors[i]; in getRow()
258 return Vectors.size(); in getNumColumns()
269 return Vectors.size(); in getNumRows()
279 return cast<VectorType>(Vectors[0]->getType()); in getVectorTy()
285 return make_range(Vectors.begin(), Vectors.end()); in columns()
289 return make_range(Vectors.begin(), Vectors.end()); in vectors()
[all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | sve2-intrinsics-fp-widening-mul-acc.ll | 6 ; FMLALB (Vectors)
37 ; FMLALT (Vectors)
68 ; FMLSLB (Vectors)
99 ; FMLSLT (Vectors)
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| H A D | sve-widen-scalable-vectortype.ll | 7 ; Vectors that need widening
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | regbank-fcmp.mir | 12 ; Vectors should always end up on a FPR.
|
| H A D | postlegalizer-combiner-anyext-to-zext.mir | 40 ; Vectors have 0 or negative 1, so we don't produce a zext.
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/ |
| H A D | vec-vararg-align.ll | 8 @.str = private unnamed_addr constant [32 x i8] c"\0AMixed Vectors, Pairs, int flt\0A\00", align 1
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | horizontal-shuffle-4.ll | 6 ; 128-bit Vectors
55 ; 256-bit Vectors
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/ |
| H A D | funnel-shift.ll | 56 ; Vectors are folded by handling each scalar element individually, so this is the equivalent of 4 s…
70 ; Vectors are folded by handling each scalar element individually, so this is the equivalent of 4 s…
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | subtract-from-one-hand-of-select.ll | 34 ; Vectors
|
| H A D | subtract-of-one-hand-of-select.ll | 34 ; Vectors
|
| H A D | narrow.ll | 35 ; Vectors (with splat constants) should get the same transform.
61 ; Vectors (with non-splat constants) should get the same transform.
|
| H A D | canonicalize-shl-lshr-to-masking.ll | 137 ; Constant Vectors
344 ; Constant Non-Splat Vectors
|
| H A D | partally-redundant-left-shift-input-masking-variant-c.ll | 35 ; Vectors
|
| H A D | partally-redundant-left-shift-input-masking-variant-e.ll | 35 ; Vectors
|
| /llvm-project-15.0.7/llvm/docs/PDB/ |
| H A D | HashTable.rst | 72 Present and Deleted Bit Vectors
|
| /llvm-project-15.0.7/clang/docs/ |
| H A D | ControlFlowIntegrityDesign.rst | 49 .. csv-table:: Bit Vectors for A, B, C
112 Stripping Leading/Trailing Zeros in Bit Vectors
121 .. csv-table:: Bit Vectors for A, B, C
128 Short Inline Bit Vectors
196 Vectors" above). The `GlobalLayoutBuilder`_ class is responsible for laying
270 Eliminating Bit Vector Checks for All-Ones Bit Vectors
515 for All-Ones Bit Vectors`_ optimizations thus simplifying the check at each
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ |
| H A D | constantfold-add-nuw-allones-to-allones.ll | 55 ; Vectors
|
| /llvm-project-15.0.7/llvm/test/CodeGen/VE/Vector/ |
| H A D | vec_broadcast.ll | 176 ; Vectors with small element types and valid element count, we expect those to be promoted.
190 ; Vectors with small element types and low element count, these are scalarized for now.
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | vector-reduce-smax.ll | 12 ;; Vectors of type i8
216 ;; Vectors of type i16
416 ;; Vectors of type i32
612 ;; Vectors of type i64
|
| H A D | vector-reduce-smin.ll | 12 ;; Vectors of type i8
216 ;; Vectors of type i16
416 ;; Vectors of type i32
612 ;; Vectors of type i64
|
| H A D | vector-reduce-umin.ll | 12 ;; Vectors of type i8
216 ;; Vectors of type i16
416 ;; Vectors of type i32
612 ;; Vectors of type i64
|
| H A D | vector-reduce-umax.ll | 12 ;; Vectors of type i8
216 ;; Vectors of type i16
416 ;; Vectors of type i32
612 ;; Vectors of type i64
|
| H A D | vector-reduce-or.ll | 12 ;; Vectors of type i32
208 ;; Vectors of type i64
|
| H A D | vector-reduce-and.ll | 12 ;; Vectors of type i32
208 ;; Vectors of type i64
|
| H A D | vector-reduce-xor.ll | 12 ;; Vectors of type i32
208 ;; Vectors of type i64
|