Searched refs:VectorList (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/clang/utils/TableGen/ |
| H A D | ClangOpenCLBuiltinEmitter.cpp | 267 std::vector<int64_t> &VectorList) const;
875 std::vector<int64_t> VectorList = in EmitQualTypeFinder() local
877 OS << " QT.reserve(" << VectorList.size() * BaseTypes.size() << ");\n" in EmitQualTypeFinder()
878 << " for (unsigned I = 0; I < " << VectorList.size() << "; I++) {\n" in EmitQualTypeFinder()
1030 std::vector<int64_t> &VectorList) const { in getTypeLists()
1034 VectorList = in getTypeLists()
1051 getTypeLists(PossibleGenType, Flags, TypeList, VectorList); in getTypeLists()
1058 VectorList.push_back(Type->getValueAsInt("VecWidth")); in getTypeLists()
1071 std::vector<int64_t> VectorList; in expandTypesInSignature() local
1074 getTypeLists(Arg, Flags, TypeList, VectorList); in expandTypesInSignature()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2135 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; in isVecListOneDByteIndexed()
2140 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; in isVecListOneDHWordIndexed()
2145 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; in isVecListOneDWordIndexed()
2150 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; in isVecListTwoDByteIndexed()
2155 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; in isVecListTwoDHWordIndexed()
2160 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; in isVecListTwoQWordIndexed()
2165 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; in isVecListTwoQHWordIndexed()
2170 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; in isVecListTwoDWordIndexed()
2175 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; in isVecListThreeDByteIndexed()
2180 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; in isVecListThreeDHWordIndexed()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 474 struct VectorListOp VectorList; member
530 VectorList = o.VectorList; in AArch64Operand()
651 return VectorList.RegNum; in getVectorListStart()
656 return VectorList.Count; in getVectorListCount()
1294 VectorList.NumElements == 0 && in isImplicitlyTypedVectorList()
1303 if (VectorList.Count != NumRegs) in isTypedVectorList()
1305 if (VectorList.RegisterKind != VectorKind) in isTypedVectorList()
2018 Op->VectorList.RegNum = RegNum; in CreateVectorList()
2019 Op->VectorList.Count = Count; in CreateVectorList()
2020 Op->VectorList.NumElements = NumElements; in CreateVectorList()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 547 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
648 defm VecListOne : VectorList<1, FPR64, FPR128>;
649 defm VecListTwo : VectorList<2, DD, QQ>;
650 defm VecListThree : VectorList<3, DDD, QQQ>;
651 defm VecListFour : VectorList<4, DDDD, QQQQ>;
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| /llvm-project-15.0.7/clang/lib/Sema/ |
| H A D | OpenCLBuiltins.td | 271 // For example, if TypeList = <int, float> and VectorList = <1, 2, 4>, then it
297 IntList VectorList = _VectorList;
298 // The VecWidth field is ignored for GenericTypes. Use VectorList instead.
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