922     struct VectorListOp VectorList;  member
2024     return Kind == k_VectorList && !VectorList.isDoubleSpaced;  in isSingleSpacedVectorList()
2028     return Kind == k_VectorList && VectorList.isDoubleSpaced;  in isDoubleSpacedVectorList()
2033     return VectorList.Count == 1;  in isVecListOneD()
2037     return isSingleSpacedVectorList() && VectorList.Count == 2 &&  in isVecListTwoMQ()
2039                VectorList.RegNum);  in isVecListTwoMQ()
2045               .contains(VectorList.RegNum));  in isVecListDPair()
2050     return VectorList.Count == 3;  in isVecListThreeD()
2055     return VectorList.Count == 4;  in isVecListFourD()
2062               .contains(VectorList.RegNum));  in isVecListDPairSpaced()
2067     return VectorList.Count == 3;  in isVecListThreeQ()
2072     return VectorList.Count == 4;  in isVecListFourQ()
2076     return isSingleSpacedVectorList() && VectorList.Count == 4 &&  in isVecListFourMQ()
2078                VectorList.RegNum);  in isVecListFourMQ()
2082     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;  in isSingleSpacedVectorAllLanes()
2086     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;  in isDoubleSpacedVectorAllLanes()
2091     return VectorList.Count == 1;  in isVecListOneDAllLanes()
2097               .contains(VectorList.RegNum));  in isVecListDPairAllLanes()
2102     return VectorList.Count == 2;  in isVecListDPairSpacedAllLanes()
2107     return VectorList.Count == 3;  in isVecListThreeDAllLanes()
2112     return VectorList.Count == 3;  in isVecListThreeQAllLanes()
2117     return VectorList.Count == 4;  in isVecListFourDAllLanes()
2122     return VectorList.Count == 4;  in isVecListFourQAllLanes()
2126     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;  in isSingleSpacedVectorIndexed()
2130     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;  in isDoubleSpacedVectorIndexed()
2135     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;  in isVecListOneDByteIndexed()
2140     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;  in isVecListOneDHWordIndexed()
2145     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;  in isVecListOneDWordIndexed()
2150     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;  in isVecListTwoDByteIndexed()
2155     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;  in isVecListTwoDHWordIndexed()
2160     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;  in isVecListTwoQWordIndexed()
2165     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;  in isVecListTwoQHWordIndexed()
2170     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;  in isVecListTwoDWordIndexed()
2175     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;  in isVecListThreeDByteIndexed()
2180     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;  in isVecListThreeDHWordIndexed()
2185     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;  in isVecListThreeQWordIndexed()
2190     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;  in isVecListThreeQHWordIndexed()
2195     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;  in isVecListThreeDWordIndexed()
2200     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;  in isVecListFourDByteIndexed()
2205     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;  in isVecListFourDHWordIndexed()
2210     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;  in isVecListFourQWordIndexed()
2215     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;  in isVecListFourQHWordIndexed()
2220     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;  in isVecListFourDWordIndexed()
3341     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));  in addVecListOperands()
3363         (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID]  in addMVEVecListOperands()
3368       if (RC_in->getRegister(I) == VectorList.RegNum)  in addMVEVecListOperands()
3377     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));  in addVecListIndexedOperands()
3378     Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));  in addVecListIndexedOperands()
3760     Op->VectorList.RegNum = RegNum;  in CreateVectorList()
3761     Op->VectorList.Count = Count;  in CreateVectorList()
3762     Op->VectorList.isDoubleSpaced = isDoubleSpaced;  in CreateVectorList()
3772     Op->VectorList.RegNum = RegNum;  in CreateVectorListAllLanes()
3773     Op->VectorList.Count = Count;  in CreateVectorListAllLanes()
3774     Op->VectorList.isDoubleSpaced = isDoubleSpaced;  in CreateVectorListAllLanes()
3784     Op->VectorList.RegNum = RegNum;  in CreateVectorListIndexed()
3785     Op->VectorList.Count = Count;  in CreateVectorListIndexed()
3786     Op->VectorList.LaneIndex = Index;  in CreateVectorListIndexed()
3787     Op->VectorList.isDoubleSpaced = isDoubleSpaced;  in CreateVectorListIndexed()
4037     OS << "<vector_list " << VectorList.Count << " * "  in print()
4038        << RegName(VectorList.RegNum) << ">";  in print()
4041     OS << "<vector_list(all lanes) " << VectorList.Count << " * "  in print()
4042        << RegName(VectorList.RegNum) << ">";  in print()
4045     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "  in print()
4046        << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";  in print()