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Searched refs:VecReg (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp686 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { in IsVecRegPair() argument
687 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || in IsVecRegPair()
688 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsVecRegPair()
691 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { in IsReverseVecRegPair() argument
692 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsReverseVecRegPair()
695 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { in IsVecRegSingle() argument
696 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31); in IsVecRegSingle()
H A DHexagonMCInstrInfo.h367 bool IsVecRegSingle(unsigned VecReg);
368 bool IsVecRegPair(unsigned VecReg);
369 bool IsReverseVecRegPair(unsigned VecReg);
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp281 Register VecReg, unsigned LaneIdx,
3484 Register VecReg = I.getOperand(1).getReg(); in selectReduction() local
3485 LLT VecTy = MRI.getType(VecReg); in selectReduction()
3492 {VecReg, VecReg}); in selectReduction()
4072 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
4089 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
4090 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
4099 Register InsertReg = VecReg; in emitExtractVectorElt()
4105 .addReg(VecReg, 0, ExtractSubReg); in emitExtractVectorElt()
4115 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder); in emitExtractVectorElt()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp2005 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2008 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
2012 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2014 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2015 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
2033 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2046 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2048 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2049 .addReg(VecReg, in expandPostRAPseudo()
2073 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
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H A DAMDGPURegisterBankInfo.cpp1929 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
1937 LLT VecTy = MRI.getType(VecReg); in foldExtractEltToCmpSelect()
1973 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldExtractEltToCmpSelect()
2027 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
2035 LLT VecTy = MRI.getType(VecReg); in foldInsertEltToCmpSelect()
2076 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldInsertEltToCmpSelect()
H A DAMDGPUInstructionSelector.cpp2762 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
2771 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2787 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2813 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
2823 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
H A DSIISelLowering.cpp3728 unsigned VecReg, in computeIndirectRegAndOffset() argument
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2469 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2470 LLT VecTy = MRI.getType(VecReg); in widenScalar()
2494 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2495 LLT VecTy = MRI.getType(VecReg); in widenScalar()