2005     Register VecReg = MI.getOperand(0).getReg();  in expandPostRAPseudo()  local
2008     assert(VecReg == MI.getOperand(1).getReg());  in expandPostRAPseudo()
2012         .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)  in expandPostRAPseudo()
2014         .addReg(VecReg, RegState::ImplicitDefine)  in expandPostRAPseudo()
2015         .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));  in expandPostRAPseudo()
2033     Register VecReg = MI.getOperand(0).getReg();  in expandPostRAPseudo()  local
2046             .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)  in expandPostRAPseudo()
2048             .addReg(VecReg, RegState::ImplicitDefine)  in expandPostRAPseudo()
2049             .addReg(VecReg,  in expandPostRAPseudo()
2073     Register VecReg = MI.getOperand(1).getReg();  in expandPostRAPseudo()  local
2085         .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)  in expandPostRAPseudo()
2086         .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));  in expandPostRAPseudo()