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Searched refs:Vec1 (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A Dvector-reductions.ll61 define i32 @TestVectorsEqual(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
92 %arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
121 define i32 @TestVectorsEqual_alt(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
151 %arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
168 define i32 @TestVectorsEqualFP(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
199 %arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
228 define i32 @TestVectorsEqualFP_alt(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
258 %arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
/llvm-project-15.0.7/clang/lib/AST/
H A DASTStructuralEquivalence.cpp810 const auto *Vec1 = cast<DependentSizedExtVectorType>(T1); in IsStructurallyEquivalent() local
812 if (!IsStructurallyEquivalent(Context, Vec1->getSizeExpr(), in IsStructurallyEquivalent()
815 if (!IsStructurallyEquivalent(Context, Vec1->getElementType(), in IsStructurallyEquivalent()
822 const auto *Vec1 = cast<DependentVectorType>(T1); in IsStructurallyEquivalent() local
824 if (Vec1->getVectorKind() != Vec2->getVectorKind()) in IsStructurallyEquivalent()
826 if (!IsStructurallyEquivalent(Context, Vec1->getSizeExpr(), in IsStructurallyEquivalent()
829 if (!IsStructurallyEquivalent(Context, Vec1->getElementType(), in IsStructurallyEquivalent()
837 const auto *Vec1 = cast<VectorType>(T1); in IsStructurallyEquivalent() local
839 if (!IsStructurallyEquivalent(Context, Vec1->getElementType(), in IsStructurallyEquivalent()
842 if (Vec1->getNumElements() != Vec2->getNumElements()) in IsStructurallyEquivalent()
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp881 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); in isNonTargetIntrinsicMatch() local
882 if (!Vec0 || !Vec1) in isNonTargetIntrinsicMatch()
884 assert(Vec0->getType() == Vec1->getType() && in isNonTargetIntrinsicMatch()
888 Constant *Elem1 = Vec1->getOperand(i); in isNonTargetIntrinsicMatch()
/llvm-project-15.0.7/clang/lib/Sema/
H A DOpenCLBuiltins.td439 def Vec1 : IntList<"Vec1", [1]>;
460 def AGenType1 : GenericType<"AGenType1", TLAll, Vec1>;
464 def AIGenType1 : GenericType<"AIGenType1", TLAllInts, Vec1>;
476 def IntLongFloatGenType1 : GenericType<"IntLongFloatGenType1", TLIntLongFloats, Vec1>;
479 TypeList<[Char, UChar, Short, UShort]>, Vec1>;
/llvm-project-15.0.7/llvm/test/Bindings/OCaml/
H A Dcore.ml1074 * CHECK: %build_extractelement = extractelement <4 x i32> %Vec1, i32 %P2
1075 * CHECK: %build_insertelement = insertelement <4 x i32> %Vec1, i32 %P1, i32 %P2
1076 …* CHECK: %build_shufflevector = shufflevector <4 x i32> %Vec1, <4 x i32> %Vec2, <4 x i32> <i32 1, …
1117 let vec1 = build_insertelement t1 p1 p2 "Vec1" atentry in
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrMMA.td606 dag Vec1 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx1));
621 Extracts.Vec1>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp2314 SDValue Vec1 = N->getOperand(1); in selectShuffle() local
2317 Results.push(TargetOpcode::COPY, ResTy, {Vec1}); in selectShuffle()
2330 Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N); in selectShuffle()
H A DHexagonISelLoweringHVX.cpp1681 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz() local
1693 DAG.getNode(ISD::SUB, dl, ResTy, {InpV, Vec1})}); in LowerHvxCttz()
/llvm-project-15.0.7/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp5012 Value *Vec1, *Vec2, *Mask; in parseFunctionBody() local
5014 if (getValueTypePair(Record, OpNum, NextValueNo, Vec1, Vec1TypeID, in parseFunctionBody()
5016 popValue(Record, OpNum, NextValueNo, Vec1->getType(), Vec1TypeID, in parseFunctionBody()
5023 if (!Vec1->getType()->isVectorTy() || !Vec2->getType()->isVectorTy()) in parseFunctionBody()
5026 I = new ShuffleVectorInst(Vec1, Vec2, Mask); in parseFunctionBody()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1871 SDValue Vec1 = IntermedVals[0].first; in ExpandBVWithShuffles() local
1885 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBVWithShuffles()
1986 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR() local
1994 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBUILD_VECTOR()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5886 SDValue Vec1 = SVN->getOperand(VecIdx1); in lowerVECTOR_SHUFFLE() local
5888 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
11224 SDValue Vec1 = Op1.getOperand(0); in performFMACombine() local
11251 if (Vec1 == Vec2 || Vec3 == Vec4) in performFMACombine()
11254 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16) in performFMACombine()
11257 if ((Vec1 == Vec3 && Vec2 == Vec4) || in performFMACombine()
11258 (Vec1 == Vec4 && Vec2 == Vec3)) { in performFMACombine()
11259 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc, in performFMACombine()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11669 SDValue Vec1 = Op.getOperand(1); in LowerINSERT_SUBVECTOR() local
11688 SDValue NewLo = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Lo, Vec1, in LowerINSERT_SUBVECTOR()
11693 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Hi, Vec1, in LowerINSERT_SUBVECTOR()
11712 Vec1 = getSVESafeBitCast(WideVT, Vec1, DAG); in LowerINSERT_SUBVECTOR()
11715 Vec1 = DAG.getNode(ISD::ANY_EXTEND, DL, WideVT, Vec1); in LowerINSERT_SUBVECTOR()
11724 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, Vec1, HiVec0); in LowerINSERT_SUBVECTOR()
11729 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, LoVec0, Vec1); in LowerINSERT_SUBVECTOR()
11744 SDValue ScalableVec1 = convertToScalableVector(DAG, VT, Vec1); in LowerINSERT_SUBVECTOR()
/llvm-project-15.0.7/llvm/docs/
H A DProgrammersManual.rst1743 PackedVector<State, 2> Vec1;
1744 Vec1.push_back(FirstCondition);
1749 Vec1 |= Vec2;
1750 return Vec1[0]; // returns 'Both'.
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp360 Value *Vec1 = nullptr; in isFixedVectorShuffle() local
391 if (!Vec1 || Vec1 == Vec) { in isFixedVectorShuffle()
392 Vec1 = Vec; in isFixedVectorShuffle()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp47553 SDValue Vec1 = N1.getOperand(0); in combineBitOpWithMOVMSK() local
47555 EVT VecVT1 = Vec1.getValueType(); in combineBitOpWithMOVMSK()
47567 DAG.getNode(VecOpc, DL, VecVT0, Vec0, DAG.getBitcast(VecVT0, Vec1)); in combineBitOpWithMOVMSK()