Home
last modified time | relevance | path

Searched refs:Vec0 (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A Dvector-reductions.ll61 define i32 @TestVectorsEqual(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
89 %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
121 define i32 @TestVectorsEqual_alt(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
148 %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
168 define i32 @TestVectorsEqualFP(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
196 %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
228 define i32 @TestVectorsEqualFP_alt(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
255 %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp880 auto *Vec0 = dyn_cast<ConstantVector>(Mask0); in isNonTargetIntrinsicMatch() local
882 if (!Vec0 || !Vec1) in isNonTargetIntrinsicMatch()
884 assert(Vec0->getType() == Vec1->getType() && in isNonTargetIntrinsicMatch()
886 for (int i = 0, e = Vec0->getNumOperands(); i != e; ++i) { in isNonTargetIntrinsicMatch()
887 Constant *Elem0 = Vec0->getOperand(i); in isNonTargetIntrinsicMatch()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrMMA.td605 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));
619 Extracts.Vec0>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp2313 SDValue Vec0 = N->getOperand(0); in selectShuffle() local
2316 Results.push(TargetOpcode::COPY, ResTy, {Vec0}); in selectShuffle()
2330 Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N); in selectShuffle()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11668 SDValue Vec0 = Op.getOperand(0); in LowerINSERT_SUBVECTOR() local
11683 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
11685 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
11711 Vec0 = getSVESafeBitCast(NarrowVT, Vec0, DAG); in LowerINSERT_SUBVECTOR()
11723 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
11728 SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
11737 if (Vec0.isUndef()) in LowerINSERT_SUBVECTOR()
11745 return DAG.getNode(ISD::VSELECT, DL, VT, PTrue, ScalableVec1, Vec0); in LowerINSERT_SUBVECTOR()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5882 SDValue Vec0 = SVN->getOperand(VecIdx0); in lowerVECTOR_SHUFFLE() local
5884 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp47552 SDValue Vec0 = N0.getOperand(0); in combineBitOpWithMOVMSK() local
47554 EVT VecVT0 = Vec0.getValueType(); in combineBitOpWithMOVMSK()
47567 DAG.getNode(VecOpc, DL, VecVT0, Vec0, DAG.getBitcast(VecVT0, Vec1)); in combineBitOpWithMOVMSK()