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Searched refs:ValReg (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp80 unsigned ValReg; in EmitTargetCodeForMemset() local
87 ValReg = X86::EAX; in EmitTargetCodeForMemset()
92 ValReg = X86::RAX; in EmitTargetCodeForMemset()
98 ValReg = X86::AX; in EmitTargetCodeForMemset()
103 ValReg = X86::AL; in EmitTargetCodeForMemset()
113 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
H A DX86FastISel.cpp83 bool X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
481 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, in X86FastEmitStore() argument
501 .addReg(ValReg).addImm(1); in X86FastEmitStore()
502 ValReg = AndResult; in X86FastEmitStore()
644 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
647 addFullAddress(MIB, AM).addReg(ValReg); in X86FastEmitStore()
691 Register ValReg = getRegForValue(Val); in X86FastEmitStore() local
692 if (ValReg == 0) in X86FastEmitStore()
695 return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned); in X86FastEmitStore()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h140 Optional<ValueAndVReg> &ValReg; member
141 GCstAndRegMatch(Optional<ValueAndVReg> &ValReg) : ValReg(ValReg) {} in GCstAndRegMatch()
143 ValReg = getIConstantVRegValWithLookThrough(Reg, MRI); in match()
144 return ValReg ? true : false; in match()
148 inline GCstAndRegMatch m_GCst(Optional<ValueAndVReg> &ValReg) { in m_GCst() argument
149 return GCstAndRegMatch(ValReg); in m_GCst()
H A DCallLowering.h309 Register extendRegister(Register ValReg, CCValAssign &VA,
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1110 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
1117 return ValReg; in extendRegister()
1121 return ValReg; in extendRegister()
1125 const LLT ValRegTy = MRI.getType(ValReg); in extendRegister()
1130 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0); in extendRegister()
1139 return ValReg; in extendRegister()
1141 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
1146 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
1151 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
H A DLegalizerHelper.cpp4029 Register ValReg = LdStMI.getReg(0); in reduceLoadStoreWidth() local
4031 LLT ValTy = MRI.getType(ValReg); in reduceLoadStoreWidth()
4046 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, in reduceLoadStoreWidth()
4103 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, in reduceLoadStoreWidth()
7179 Register ValReg = MI.getOperand(ValRegIndex).getReg(); in lowerReadWriteRegister() local
7180 const LLT Ty = MRI.getType(ValReg); in lowerReadWriteRegister()
7189 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
7191 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp380 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
383 .addReg(ValReg) in insertSext()
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
386 .addReg(ValReg) in insertSext()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp298 createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, in createNewIdReg() argument
301 SPIRVType *SpvType = GR.getSPIRVTypeForVReg(ValReg); in createNewIdReg()
311 if (MRI.getType(ValReg).isPointer()) { in createNewIdReg()
315 } else if (MRI.getType(ValReg).isVector()) { in createNewIdReg()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp1949 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1953 .addReg(ValReg) in emitInstruction()
1960 .addReg(ValReg) in emitInstruction()
1963 .addReg(ValReg) in emitInstruction()
1970 .addReg(ValReg) in emitInstruction()
2015 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
2019 .addReg(ValReg) in emitInstruction()
2029 .addReg(ValReg) in emitInstruction()
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp645 Optional<ValueAndVReg> ValReg; in TEST_F() local
648 EXPECT_TRUE(mi_match(IntOne, *MRI, m_GCst(ValReg))); in TEST_F()
649 EXPECT_EQ(IntOne, ValReg->VReg); in TEST_F()
652 EXPECT_FALSE(mi_match(FPOne, *MRI, m_GCst(ValReg))); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1087 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
1088 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
1100 MIRBuilder.buildMerge(ValReg, {NewI->getOperand(0), NewI->getOperand(1)}); in legalizeLoadStore()
1132 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1136 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
H A DAArch64InstructionSelector.cpp2800 Register ValReg = LdSt.getReg(0); in select() local
2801 if (MRI.getType(ValReg).getSizeInBits() == 64 && MemSizeInBits != 64) { in select()
2824 const Register ValReg = LdSt.getReg(0); in select() local
2825 const LLT ValTy = MRI.getType(ValReg); in select()
2826 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
2839 .addReg(ValReg, 0, SubReg) in select()
5793 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic() local
5807 auto PAC = MIB.buildInstr(Opcode, {DstReg}, {ValReg}); in selectIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1362 Register ValReg = MI.getOperand(3).getReg(); in selectDSOrderedIntrinsic() local
1365 .addReg(ValReg) in selectDSOrderedIntrinsic()
2763 Register ValReg = MI.getOperand(2).getReg(); in selectG_INSERT_VECTOR_ELT() local
2767 LLT ValTy = MRI->getType(ValReg); in selectG_INSERT_VECTOR_ELT()
2772 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2789 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2814 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
2824 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
H A DAMDGPULegalizerInfo.cpp2647 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoad() local
2648 LLT ValTy = MRI.getType(ValReg); in legalizeLoad()
2683 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad()
2691 B.buildExtract(ValReg, WideLoad, 0); in legalizeLoad()
2696 B.buildDeleteTrailingVectorElements(ValReg, WideLoad); in legalizeLoad()