Searched refs:ValLoc (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 284 SmallVectorImpl<unsigned> &ValLoc, in getNoopInput() argument
332 if (ValLoc.size() >= InsertLoc.size() && in getNoopInput()
333 std::equal(InsertLoc.begin(), InsertLoc.end(), ValLoc.rbegin())) { in getNoopInput()
337 ValLoc.resize(ValLoc.size() - InsertLoc.size()); in getNoopInput()
349 ValLoc.append(ExtractLoc.rbegin(), ExtractLoc.rend()); in getNoopInput()
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| /llvm-project-15.0.7/llvm/lib/AsmParser/ |
| H A D | LLParser.cpp | 7444 Value *Ptr, *Val; LocTy PtrLoc, ValLoc; in parseAtomicRMW() local
7491 parseTypeAndValue(Val, ValLoc, PFS) || in parseAtomicRMW()
7502 return error(ValLoc, "atomicrmw value and pointer type do not match"); in parseAtomicRMW()
7509 ValLoc, in parseAtomicRMW()
7515 return error(ValLoc, "atomicrmw " + in parseAtomicRMW()
7521 return error(ValLoc, "atomicrmw " + in parseAtomicRMW()
7531 return error(ValLoc, "atomicrmw operand must be power-of-two byte-sized" in parseAtomicRMW()
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| /llvm-project-15.0.7/llvm/lib/TableGen/ |
| H A D | TGParser.cpp | 2780 SMLoc ValLoc = Lex.getLoc(); in ParseDeclaration() local
2783 SetValue(CurRec, ValLoc, DeclName, None, Val)) in ParseDeclaration()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 6431 SMLoc ValLoc = getLoc(); in parseCnt() local
6452 Error(ValLoc, "too large value for " + CntName); in parseCnt()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3031 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg, in lowerMasksToReg()
3034 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) || in lowerMasksToReg()
3035 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) { in lowerMasksToReg()
3041 if (ValLoc == MVT::i32) in lowerMasksToReg()
3042 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy); in lowerMasksToReg()
3046 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) || in lowerMasksToReg()
3047 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) { in lowerMasksToReg()
3050 return DAG.getBitcast(ValLoc, ValArg); in lowerMasksToReg()
3053 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg); in lowerMasksToReg()
3401 const EVT &ValLoc, const SDLoc &Dl, in lowerRegToMasks() argument
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