Lines Matching refs:ValLoc
3026 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc, in lowerMasksToReg() argument
3031 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg, in lowerMasksToReg()
3034 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) || in lowerMasksToReg()
3035 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) { in lowerMasksToReg()
3041 if (ValLoc == MVT::i32) in lowerMasksToReg()
3042 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy); in lowerMasksToReg()
3046 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) || in lowerMasksToReg()
3047 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) { in lowerMasksToReg()
3050 return DAG.getBitcast(ValLoc, ValArg); in lowerMasksToReg()
3053 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg); in lowerMasksToReg()
3401 const EVT &ValLoc, const SDLoc &Dl, in lowerRegToMasks() argument
3410 assert(ValLoc == MVT::i64 && "Expecting only i64 locations"); in lowerRegToMasks()