Home
last modified time | relevance | path

Searched refs:VT0 (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transforms.mlir338 // CHECK: %[[VT0:.*]] = vector.transfer_read %[[ARG0]][%[[C0]], %[[C0]]], {{.*}} : memref<4…
346 // CHECK: %[[CMP0:.*]] = arith.cmpf ult, %[[VT0]], %[[VT4]] : vector<2x2xf32>
350 // CHECK: %[[VT0:.*]] = vector.transfer_read %[[ARG0]][%[[C0]], %[[C0]]], {{.*}} : memref<4…
358 // CHECK: %[[SEL0:.*]] = arith.select %[[CMP0]], %[[VT0]], %[[VT4]] : vector<2x2xi1>, vecto…
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp75 for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp5202 EVT VT0 = getSetCCResultType(getSETCCOperandType(SETCC0)); in WidenVSELECTMask() local
5204 unsigned ScalarBits0 = VT0.getScalarSizeInBits(); in WidenVSELECTMask()
5212 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTMask()
5213 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask()
5222 MaskVT = VT0; in WidenVSELECTMask()
5225 SETCC0 = convertMask(SETCC0, VT0, MaskVT); in WidenVSELECTMask()
H A DDAGCombiner.cpp10347 EVT VT0 = N0.getValueType(); in visitSELECT() local
10364 if (VT0 == MVT::i1) { in visitSELECT()
10486 SDVTList VTs = DAG.getVTList(VT, VT0); in visitSELECT()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3603 EVT VT0 = Op.getValue(0).getValueType(); in lowerADDSUBCARRY() local
3606 if (VT0 != MVT::i32 && VT0 != MVT::i64) in lowerADDSUBCARRY()
3615 SDVTList VTs = DAG.getVTList(VT0, VT1); in lowerADDSUBCARRY()
3617 SDValue Sum = DAG.getNode(Opcode, DL, DAG.getVTList(VT0, MVT::Glue), OpLHS, in lowerADDSUBCARRY()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp38741 EVT VT0 = BC0.getValueType(); in canonicalizeShuffleMaskWithHorizOp() local
38743 if (VT0.getSizeInBits() != RootSizeInBits || llvm::any_of(BC, [&](SDValue V) { in canonicalizeShuffleMaskWithHorizOp()
38744 return V.getOpcode() != Opcode0 || V.getValueType() != VT0; in canonicalizeShuffleMaskWithHorizOp()
38760 int NumElts = VT0.getVectorNumElements(); in canonicalizeShuffleMaskWithHorizOp()
38761 int NumLanes = VT0.getSizeInBits() / 128; in canonicalizeShuffleMaskWithHorizOp()
38780 return DAG.getUNDEF(VT0); in canonicalizeShuffleMaskWithHorizOp()
38782 return getZeroVector(VT0.getSimpleVT(), Subtarget, DAG, DL); in canonicalizeShuffleMaskWithHorizOp()
38796 return DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
38826 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
38842 if (Mask.size() == VT0.getVectorNumElements()) { in canonicalizeShuffleMaskWithHorizOp()
[all …]