Searched refs:VRRC (Results 1 – 10 of 10) sorted by relevance
32 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers34 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers37 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers39 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers42 ; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers44 ; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers47 ; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 16 registers49 ; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 16 registers
102 ; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers104 ; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers106 ; CHECK-NEXT: LV: The target has 32 registers of RISCV::VRRC register class233 ; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers235 ; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers237 ; CHECK-NEXT: LV: The target has 32 registers of RISCV::VRRC register class
911 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;947 def : Pat<(f128 (bitconvert (v16i8 VRRC:$src))), (f128 VRRC:$src)>;948 def : Pat<(f128 (bitconvert (v8i16 VRRC:$src))), (f128 VRRC:$src)>;949 def : Pat<(f128 (bitconvert (v4i32 VRRC:$src))), (f128 VRRC:$src)>;950 def : Pat<(f128 (bitconvert (v4f32 VRRC:$src))), (f128 VRRC:$src)>;951 def : Pat<(f128 (bitconvert (v2f64 VRRC:$src))), (f128 VRRC:$src)>;953 def : Pat<(v16i8 (bitconvert (f128 VRRC:$src))), (v16i8 VRRC:$src)>;954 def : Pat<(v8i16 (bitconvert (f128 VRRC:$src))), (v8i16 VRRC:$src)>;955 def : Pat<(v4i32 (bitconvert (f128 VRRC:$src))), (v4i32 VRRC:$src)>;956 def : Pat<(v4f32 (bitconvert (f128 VRRC:$src))), (v4f32 VRRC:$src)>;[all …]
847 ClassID == VRRC || ClassID == VSXRC); in getNumberOfRegisters()849 assert(ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC); in getNumberOfRegisters()852 assert(ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC); in getNumberOfRegisters()858 return ST->hasVSX() ? VSXRC : VRRC; in getRegisterClassForType()864 return VRRC; in getRegisterClassForType()879 case VRRC: return "PPC::VRRC"; in getRegisterClassName()
2535 (COPY_TO_REGCLASS $A, VRRC)>;2537 (COPY_TO_REGCLASS $A, VRRC)>;2539 (COPY_TO_REGCLASS $A, VRRC)>;2541 (COPY_TO_REGCLASS $A, VRRC)>;2553 (COPY_TO_REGCLASS $A, VRRC)>;2555 (COPY_TO_REGCLASS $A, VRRC)>;2557 (COPY_TO_REGCLASS $A, VRRC)>;2559 (COPY_TO_REGCLASS $A, VRRC)>;2562 (COPY_TO_REGCLASS $A, VRRC)>;2564 (COPY_TO_REGCLASS $A, VRRC)>;[all …]
94 GPRRC, FPRRC, VRRC, VSXRC enumerator
1180 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;1950 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;1952 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;1954 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;1963 (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;1965 (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>;1967 (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>;1969 (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>;1980 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;1982 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;[all …]
350 def VRRC : RegisterClass<"PPC",363 (add VSLRC, VRRC)>;507 def vrrc : RegisterOperand<VRRC> {
225 enum RISCVRegisterClass { GPRRC, FPRRC, VRRC }; enumerator236 case RISCVRegisterClass::VRRC: in getNumberOfRegisters()248 return RISCVRegisterClass::VRRC;268 case RISCVRegisterClass::VRRC: in getRegisterClassName()
228 ;CHECK: LV(REG): RegisterClass: PPC::VRRC, 2 registers