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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dstatepoint-vreg-details.ll28 ; CHECK-VREG: $rdi = COPY %1
142 ; CHECK-VREG: RET 0
209 ; CHECK-VREG: bb.0.entry:
249 ; CHECK-VREG: bb.0.entry:
264 ; CHECK-VREG: bb.1.left:
267 ; CHECK-VREG: bb.2.right:
287 ; CHECK-VREG: bb.0.entry:
342 ; CHECK-VREG: RET 0
357 ;CHECK-VREG: bb.0.entry:
387 ; CHECK-VREG-NOT: COPY [[VREG]]
[all …]
H A Dstatepoint-vreg-unlimited-tied-opnds.ll1 …c -max-registers-for-gc-values=18 -stop-before greedy < %s | FileCheck --check-prefix=CHECK-VREG %s
14 ; CHECK-VREG-LABEL: test_spill
15 ; CHECK-VREG: %5:gr64 = COPY $r9
16 ; CHECK-VREG: %4:gr64 = COPY $r8
17 ; CHECK-VREG: %3:gr64 = COPY $rcx
18 ; CHECK-VREG: %2:gr64 = COPY $rdx
19 ; CHECK-VREG: %1:gr64 = COPY $rsi
20 ; CHECK-VREG: %0:gr64 = COPY $rdi
24 ; CHECK-VREG: %9:gr64 = MOV64rm %fixed-stack.8, 1, $noreg, 0, $noreg :: (load (s64) from %fixed…
34 ; CHECK-VREG: %38:gr32 = MOV32rm %0, 1, $noreg, 4, $noreg :: (load (s32) from %ir.gep00, addrsp…
[all …]
H A Dtail-dup-debugloc.ll7 ; CHECK: [[VREG:%[^ ]+]]:gr64 = COPY $rdi
8 ; CHECK: TEST64rr [[VREG]], [[VREG]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.sbfe.ll79 ; GCN: buffer_store_dword [[VREG]],
174 ; GCN: buffer_store_dword [[VREG]],
185 ; GCN: buffer_store_dword [[VREG]],
196 ; GCN: buffer_store_dword [[VREG]],
207 ; GCN: buffer_store_dword [[VREG]],
218 ; GCN: buffer_store_dword [[VREG]],
229 ; GCN: buffer_store_dword [[VREG]],
240 ; GCN: buffer_store_dword [[VREG]],
251 ; GCN: buffer_store_dword [[VREG]],
262 ; GCN: buffer_store_dword [[VREG]],
[all …]
H A Dtrunc-store-i1.ll8 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
9 ; GCN: buffer_store_byte [[VREG]],
28 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
29 ; GCN: buffer_store_byte [[VREG]],
H A Dmai-inline.ll5 ; GFX908: v_accvgpr_read [[VREG:v[0-9]+]], [[AREG]]
6 ; GFX908: global_store_dword v{{[0-9]+}}, [[VREG]], s{{\[[0-9]+:[0-9]+\]}}
H A Dtrunc.ll58 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
68 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Dselect-fp-const.mir35 …; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from con…
38 ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
66 …; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load (s64) from con…
69 ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
98 ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 /* CC::al */, $noreg
99 …; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from cons…
102 ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
131 ; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14 /* CC::al */, $noreg
132 …; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load (s64) from cons…
135 ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
H A Darm-irtranslator.ll63 ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
64 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
107 ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
108 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
H A Dselect-fp.mir63 ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY $d0
69 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
/llvm-project-15.0.7/llvm/test/Instrumentation/DataFlowSanitizer/
H A Darray.ll261 ; FAST: %[[#VREG+1]] = insertelement <8 x i[[#SBITS]]> %[[#VREG]], i[[#SBITS]] %[[#R+33]], i32 1
262 ; FAST: %[[#VREG+2]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+1]], i[[#SBITS]] %[[#R+33]], i32 2
263 ; FAST: %[[#VREG+3]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+2]], i[[#SBITS]] %[[#R+33]], i32 3
264 ; FAST: %[[#VREG+4]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+3]], i[[#SBITS]] %[[#R+33]], i32 4
265 ; FAST: %[[#VREG+5]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+4]], i[[#SBITS]] %[[#R+33]], i32 5
266 ; FAST: %[[#VREG+6]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+5]], i[[#SBITS]] %[[#R+33]], i32 6
267 ; FAST: %[[#VREG+7]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+6]], i[[#SBITS]] %[[#R+33]], i32 7
269 ; FAST: %[[#VREG+9]] = getelementptr <8 x i[[#SBITS]]>, <8 x i[[#SBITS]]>* %[[#VREG+8]], i32 0
270 ; FAST: store <8 x i[[#SBITS]]> %[[#VREG+7]], <8 x i[[#SBITS]]>* %[[#VREG+9]], align [[#SBYTES]]
271 ; FAST: %[[#VREG+10]] = getelementptr <8 x i[[#SBITS]]>, <8 x i[[#SBITS]]>* %[[#VREG+8]], i32 1
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h37 VREG = 3 ///< Value is a virtual register. enumerator
67 assert(kind == VREG); in getVReg()
78 return SDDbgOperand(VReg, VREG); in fromVReg()
93 case VREG:
122 assert((Kind == VREG || Kind == FRAMEIX) && in SDDbgOperand()
124 if (kind == VREG) in SDDbgOperand()
H A DInstrEmitter.cpp727 case SDDbgOperand::VREG: in AddDbgValueLocationOps()
810 if (DbgOperand.getKind() == SDDbgOperand::VREG) { in EmitDbgInstrRef()
H A DSelectionDAGDumper.cpp874 case SDDbgOperand::VREG: in print()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dmemcpy_dereferenceable.ll6 ; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
8 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
9 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
39 ; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
41 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
42 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
H A Dppc32-pic.ll27 ; SMALL-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
28 ; SMALL-DAG: lwz {{[0-9]+}}, 0([[VREG]])
H A Dppc32-pic-large.ll44 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
45 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-args-05.ll23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
24 ; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/X86/
H A Dremove-debug-2.ll15 ; CHECK: [[VREG:%[^ ]+]] = select
16 ; CHECK: store i32 [[VREG]],{{.*}} !dbg [[storeLoc:![0-9]+]]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dswp-prolog-phi.ll8 ; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh)
9 ; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
H A Dswp-epilog-phi7.ll9 ; CHECK: [[VREG:v([0-9]+)]]{{.*}} = {{.*}}vmem(r{{[0-9]+}}++#1)
13 ; CHECK: [[VREG1:v([0-9]+)]] = [[VREG]]
14 ; CHECK: [[VREG]] = v{{[0-9]+}}
16 ; CHECK: = vlalign([[VREG]],[[VREG1]],#1)
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/
H A Dsink-leaves-undef.mir95 ; CHECK: %[[VREG:[0-9]+]]:gr32 = MOV32rm
96 ; CHECK-NEXT: DBG_VALUE %[[VREG]], $noreg, ![[VARNUM]]
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Ddbg-val-list-dangling.ll25 ; CHECK-DAG: DBG_VALUE %[[VREG:[0-9]]], $noreg, ![[C]], !DIExpression(), debug-location